Direct-view mems display devices and methods for generating images thereon

ABSTRACT

A direct-view display includes an array of MEMS light modulators and a control matrix formed on a transparent substrate, where each light modulator can be driven into at least two states, and a controller for controlling the states of each light modulator in the array. The control matrix transmits data and actuation voltages to the array. The controller includes an input, a processor, a memory, and an output. The input receives image data encoding an image frame for display. The processor derives a plurality of sub-frame data sets from the image data, where each sub-frame data set indicates desired states of light modulators in multiple rows and multiple columns of the array. The memory stores the plurality of sub-frame data sets. The output outputs the plurality of sub-frame data sets according to an output sequence to drive light modulators into the states indicated in the sub-frame data sets.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/643,042, filed Dec. 19, 2006, which claims priority to and thebenefit of U.S. Patent Application No. 60/751,909, filed Dec. 19, 2005,now abandoned, and U.S. Patent Application No. 60/776,367, filed Feb.24, 2006, now abandoned, and is also a continuation-in-part of U.S.patent application Ser. No. 11/361,294, filed Feb. 23, 2006, nowabandoned, and which claims priority to and the benefit of U.S. PatentApplication No. 60/676,053, filed Apr. 29, 2005, now abandoned, and U.S.Patent Application No. 60/655,827, filed Feb. 23, 2005, now abandoned.The disclosures of all of the foregoing are incorporated herein byreference in their entirety.

FIELD OF THE INVENTION

In general, the invention relates to the field of imaging displays, inparticular, the invention relates to controller circuits and processesfor controlling light modulators incorporated into imaging displays.

BACKGROUND OF THE INVENTION

Displays built from mechanical light modulators are an attractivealternative to displays based on liquid crystal technology. Mechanicallight modulators are fast enough to display video content with goodviewing angles and with a wide range of color and grey scale. Mechanicallight modulators have been successful in projection displayapplications. Direct-view displays using mechanical light modulatorshave not yet demonstrated sufficiently attractive combinations ofbrightness and low power.

In contrast to projection displays in which switching circuitry andlight modulators can be built on relatively small die cut from siliconsubstrates, most direct-view displays require the fabrication of lightmodulators on much larger substrates. In addition, in many cases,particularly for backlit direct view displays, both the controlcircuitry and the light modulators are preferably formed on transparentsubstrates. As a result, many typical semiconductor manufacturingprocesses are inapplicable, and switching circuits often need to bere-designed accordingly. A need remains for MEMS direct-view displaysthat incorporate display processes in conjunction with switchingcircuitry that yield detailed images along with rich levels of grayscaleand contrast.

SUMMARY

There is a need in the art for fast, bright, low-powered mechanicallyactuated direct-view displays. Specifically there is a need fordirect-view displays built on transparent substrates that can be drivenat high speeds and at low voltages for improved image quality andreduced power consumption.

In one aspect of the invention, a direct-view display includes an arrayof MEMS light modulators and a control matrix both formed on atransparent substrate, where each of the light modulators can be driveninto at least two states. The control matrix transmits data andactuation voltages to the array and may include, for each lightmodulator, a transistor and a capacitor. The direct-view display alsoincludes a controller for controlling the states of each of the lightmodulators in the array. The controller includes an input, a processor,a memory, and an output. The input receives image data encoding an imageframe for display on the direct-view display. The processor derives aplurality of sub-frame data sets from the image data. Each sub-framedata set indicates desired states of light modulators in multiple rowsand multiple columns of the array. The memory stores the plurality ofsub-frame data sets. The output outputs the plurality of sub-frame datasets according to an output sequence to drive light modulators into thestates indicated in the sub-frame data sets. The plurality of sub-framedata sets may include distinct sub-frame data sets for at least two ofat least three color components of the image frame or for four colorcomponents of the image frame, where the four color components mayconsist of red, green, blue, and white.

In one embodiment, the output sequence includes a plurality of eventscorresponding to the sub-frame data sets. The controller storesdifferent time values associated with events corresponding to at leasttwo sub-frame data sets. The time values may be selected to preventillumination of the array while the modulators change states and maycorrelate to a brightness of a sub-frame image resulting from anoutputting of a sub-frame data set of the plurality of sub-frame datasets. The direct-view display may include a plurality of lamps, in whichcase the controller may store time values associated with lampillumination events and/or lamp extinguishing events included in theoutput sequence. The output sequence may include addressing events,where the controller stores time values associated with the addressingevents.

In another embodiment, the output sequence is stored at least in part inmemory. The direct-view display may include a data link to an externalprocessor for receiving changes to the output sequence. The direct-viewdisplay may include a plurality of lamps, where the output sequenceincludes a lamp illumination sequence. The lamp illumination sequencemay include data corresponding to the length of time and/or intensitywith which lamps are illuminated in association with sub-frame data setsoutput in the output sequence. The length of time that a lamp isilluminated for each sub-frame data set in the lamp illuminationsequence is preferably less than or equal to 4 milliseconds.

In another embodiment, the processor derives the plurality of sub-framedata sets by decomposing the image frame into a plurality of sub-frameimages and assigning a weight to each sub-frame image of the pluralityof sub-frame images. The controller may cause a sub-frame image to beilluminated for a length of time and/or with an illumination intensityproportional to the weight assigned to the sub-frame image. Theprocessor may assign the weight according to a coding scheme. In oneimplementation, the coding scheme is a binary coding scheme, thesub-frame data sets are bitplanes, and each color component of the imageframe is decomposed into at least a most significant sub-frame image anda next most significant sub-frame image. The most-significant sub-frameimage may contribute to a displayed image frame twice as much as thenext most significant sub-frame image. According to the output sequence,the bitplane corresponding to the most significant sub-image of at leastone color component of the image frame may be output at two distincttimes which may be separated by no more than 25 milliseconds. The lengthof time between a first time the bitplane corresponding to the mostsignificant sub-frame image of a color component of the image frame isoutput and a second time the bitplane corresponding to the mostsignificant sub-frame image of the color component is output ispreferably within 10% of the length of time between the second time thebitplane corresponding to the most significant sub-frame image of thecolor component is output and a subsequent time at which a sub-frameimage corresponding to a most significant sub-frame image of the colorcomponent is output.

In another embodiment, at least one sub-frame data set corresponding toa first color component of the image frame is output before at least onesub-frame data set corresponding to a second color component of theimage frame, and at least one sub-frame data set corresponding to thefirst color component of the image frame is output after at least onesub-frame data set corresponding to the second color component of theimage frame. Lamps of at least two different colors may be illuminatedto display a single sub-frame image corresponding to a single sub-framedata set, where a lamp of one of the colors may be illuminated with asubstantially greater intensity than lamps of the other colors.

In another embodiment, the direct-view display includes a memory forstoring a plurality of alternative output sequences and may include anoutput sequence switching module for switching between the outputsequence and the plurality of alternative output sequences. The outputsequence switching module may respond to the processor, to a userinterface included in the direct-view display, and/or to instructionsreceived from a second processor, external to the controller, includedin the device in which the direct-view display is incorporated. The userinterface may be a manual switch.

In another embodiment, the direct-view display includes a sequenceparameter calculation module for deriving changes to the outputsequence. Based on characteristics of a received image frame, thesequence parameter calculation module may derive changes to the outputsequence, to timing values stored in relation to events included in theoutput sequence, and/or to sub-frame data sets. The direct-view displaymay include a plurality of lamps, in which case the sequence parametercalculation module may derive changes to lamp intensity values stored inrelation to lamp illumination events included in the output sequence.

In another embodiment, the array of light modulators includes aplurality of independently actuatable banks of light modulators. Thecontrol matrix may include a plurality of global actuationinterconnects, where each global actuation interconnect corresponds to arespective bank of light modulators. The plurality of banks may belocated adjacent one another in the array. Alternatively, each bank oflight modulator may include a plurality of rows in the array, where thebanks are interwoven with one another in the array. In oneimplementation, the display of a sub-frame image corresponding to aparticular significance and color component in one of the banks is nomore than 25 ms from a subsequent display of a sub-frame imagecorresponding to the significance value and color component, and is nomore than 25 ms after a prior display of a sub-frame image correspondingto the significance and color component in the other of the banks.

In another embodiment, the light modulators include shutters. Theshutters may selectively reflect light and/or selectively allow lowlight to pass through corresponding apertures to form the image frame.The shutters may be driven transverse to the substrate. In anotherembodiment, the light modulators are reflective light modulators. Inanother embodiment, the light modulators selectively allow the passageof light towards a viewer. In another embodiment, a light guide ispositioned proximate the array of light modulators.

In another embodiment, the output sequence includes a plurality ofglobal actuation events. The direct-view display may include a globalactuation interconnect coupled to the array of light modulators forcausing light modulators in multiple rows and multiple columns of thearray of light modulators to actuate substantially simultaneously.

In another aspect of the invention, a direct-view display includes anarray of MEMS light modulators and a control matrix both formed on atransparent substrate, where each of the light modulators can be driveninto at least two states, and lamps of at least three colors. Thecontrol matrix transmits data and actuation voltages to the array. Thedirect-view display also includes a controller for controlling thestates of each of the light modulators in the array. The controller alsocontrols the illumination of lamps to illuminate the array of lightmodulators with lamps of at least two colors at the same time to form aportion of an image. At least one of the colors illuminating the arrayof light modulators may be of greater intensity than the other colors.

Another aspect of the invention includes a method for displaying animage frame on a direct-view display. The method includes the steps ofreceiving image data encoding the image frame; deriving a plurality ofsub-frame data sets from the image data; storing the plurality ofsub-frame data sets in a memory; and outputting the plurality ofsub-frame data sets according to an output sequence. Each sub-frame dataset indicates desired states of MEMS light modulators in multiple rowsand multiple columns of a light modulator array formed on a transparentsubstrate. The step of outputting the plurality of sub-frame data setsdrives the MEMS light modulators into the desired states indicated ineach sub-frame data set and includes transmitting data and actuationvoltages to the light modulator array via a control matrix formed on thetransparent substrate.

In another aspect of the invention, a direct-view display includes anarray of MEMS light modulators and a control matrix both formed on atransparent substrate, wherein each of the light modulators can bedriven into at least two states. The control matrix transmits data andactuation voltages to the array. The direct-view display also includes acontroller for controlling the states of each of the light modulators inthe array. The controller also controls the illumination of lamps of atleast four colors to display an image. The lamps may include at least ared lamp, a green lamp, a blue lamp, and a white lamp. The lamps mayinclude at least a red lamp, a green lamp, a blue lamp, and a yellowlamp. The direct-view display may include a processor for translatingthree color image data into four color image data.

Another aspect of the invention includes a method for displaying animage on a direct-view display. The method includes the steps ofcontrolling states of MEMS light modulators in a light modulator arrayformed on a transparent substrate, where each of the MEMS lightmodulators can be driven into at least two states; transmitting data andactuation voltages to the light modulator array via a control matrixformed on the transparent substrate; and controlling the illumination oflamps of at least four colors to display the image.

BRIEF DESCRIPTION

In the detailed description which follows, reference will be made to theattached drawings, in which:

FIG. 1 is a schematic diagram of a direct-view MEMS-based displayaccording to an illustrative embodiment of the invention;

FIG. 2A is a perspective view of an illustrative shutter-based lightmodulator suitable for incorporation into the direct-view MEMS-baseddisplay of FIG. 1, according to an illustrative embodiment of theinvention;

FIG. 2B is a cross-sectional view of a rollershade-based light modulatorsuitable for incorporation into the direct-view MEMS-based display ofFIG. 1, according to an illustrative embodiment of the invention;

FIG. 2C is a cross sectional view of a light-tap-based light modulatorsuitable for incorporation into the direct-view MEMS-based display ofFIG. 1, according to an illustrative embodiment of the invention;

FIG. 2D is a cross sectional view of an electrowetting-based lightmodulator suitable for incorporation into the direct-view MEMS-baseddisplay of FIG. 1, according to an illustrative embodiment of theinvention;

FIG. 3A is a schematic diagram of a control matrix suitable forcontrolling the light modulators incorporated into the direct-viewMEMS-based display of FIG. 1, according to an illustrative embodiment ofthe invention;

FIG. 3B is a perspective view of an array of shutter-based lightmodulators connected to the control matrix of FIG. 3A, according to anillustrative embodiment of the invention;

FIG. 3C illustrates a portion of a direct view display that includes thearray of light modulators depicted in FIG. 3B disposed on top of abacklight, according to an illustrative embodiment of the invention;

FIG. 3D is a schematic diagram of another suitable control matrix forinclusion in the direct-view MEMS-based display of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 4 is a timing diagram for a method of displaying an image on adisplay using a field sequential color technique;

FIG. 5 is a timing diagram for a method of displaying an image on adisplay using a time-division gray scale technique;

FIG. 6A is a schematic diagram of a digital image signal received by adisplay device, according to an illustrative embodiment of theinvention;

FIG. 6B is a schematic diagram of a memory buffer useful for convertinga received image signal into a bitplane, according to an illustrativeembodiment of the invention;

FIG. 6C is a schematic diagram of portions of two bitplanes, accordingto an illustrative embodiment of the invention;

FIG. 7 is a block diagram of a display apparatus, according to anillustrative embodiment of the invention;

FIG. 8 is a flow chart of a method of displaying images suitable for useby the display apparatus of FIG. 6, according to an illustrativeembodiment of the invention;

FIG. 9 is a more detailed flow chart of a portion of a firstimplementation of the method of FIG. 7, according to an illustrativeembodiment of the invention;

FIG. 10 is a timing diagram illustrating the timing of various imageformation events in the method of FIG. 9, according to an illustrativeembodiment of the invention;

FIG. 11 is a more detailed flow chart of a portion of a secondimplementation of the method of FIG. 8, according to an illustrativeembodiment of the invention;

FIG. 12 is a timing diagram illustrating the timing of various imageformation events in a first implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 13 is a timing diagram illustrating the timing of various imageformation events in a second implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 14A is a timing diagram illustrating the timing of various imageformation events in a third implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 14B is a timing diagram illustrating the timing of various imageformation events in a fourth implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 14C depicts various pulse profiles for lamps, according to anillustrative embodiment of the invention;

FIG. 15 is a timing diagram illustrating the timing of various imageformation events in a fourth implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 16 is a timing diagram illustrating the timing of various imageformation events in a fifth implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 17 is a timing diagram illustrating the timing of various imageformation events in a sixth implementation of the method of FIG. 11,according to an illustrative embodiment of the invention;

FIG. 18 is a more detailed flow chart of a portion of a thirdimplementation of the method of FIG. 8, according to an illustrativeembodiment of the invention;

FIG. 19 is a timing diagram illustrating the timing of various imageformation events in an implementation of the method of FIG. 18,according to an illustrative embodiment of the invention;

FIG. 20 is a block diagram of a controller suitable for inclusion in thedisplay apparatus of FIG. 1, according to an illustrative embodiment ofthe invention;

FIG. 21 is a flow chart of a method of displaying an image suitable foruse by the controller of FIG. 20, according to an illustrativeembodiment of the invention;

FIG. 22 is a block diagram of a second controller suitable for inclusionin the display apparatus of FIG. 1, according to an illustrativeembodiment of the invention; and

FIG. 23 is a flow chart of a method of displaying an image suitable foruse by the controller of FIG. 22, according to an illustrativeembodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 is a schematic diagram of a direct-view MEMS-based displayapparatus 100, according to an illustrative embodiment of the invention.The display apparatus 100 includes a plurality of light modulators 102a-102 d (generally “light modulators 102”) arranged in rows and columns.In the display apparatus 100, light modulators 102 a and 102 d are inthe open state, allowing light to pass. Light modulators 102 b and 102 care in the closed state, obstructing the passage of light. Byselectively setting the states of the light modulators 102 a-102 d, thedisplay apparatus 100 can be utilized to form an image 104 for a backlitdisplay, if illuminated by a lamp or lamps 105. In anotherimplementation, the apparatus 100 may form an image by reflection ofambient light originating from the front of the apparatus. In anotherimplementation, the apparatus 100 may form an image by reflection oflight from a lamp or lamps positioned in the front of the display, i.e.by use of a frontlight.

In the display apparatus 100, each light modulator 102 corresponds to apixel 106 in the image 104. In other implementations, the displayapparatus 100 may utilize a plurality of light modulators to form apixel 106 in the image 104. For example, the display apparatus 100 mayinclude three color-specific light modulators 102. By selectivelyopening one or more of the color-specific light modulators 102corresponding to a particular pixel 106, the display apparatus 100 cangenerate a color pixel 106 in the image 104. In another example, thedisplay apparatus 100 includes two or more light modulators 102 perpixel 106 to provide grayscale in an image 104. With respect to animage, a “pixel” corresponds to the smallest picture element defined bythe resolution of image. With respect to structural components of thedisplay apparatus 100, the term “pixel” refers to the combinedmechanical and electrical components utilized to modulate the light thatforms a single pixel of the image.

Display apparatus 100 is a direct-view display in that it does notrequire imaging optics that are necessary for projection applications.In a projection display, the image formed on the surface of the displayapparatus is projected onto a screen or onto a wall. The displayapparatus is substantially smaller than the projected image. In a directview display, the user sees the image by looking directly at the displayapparatus, which contains the light modulators and optionally abacklight or front light for enhancing brightness and/or contrast seenon the display.

Direct-view displays may operate in either a transmissive or reflectivemode. In a transmissive display, the light modulators filter orselectively block light which originates from a lamp or lamps positionedbehind the display. The light from the lamps is optionally injected intoa lightguide or “backlight” so that each pixel can be uniformlyilluminated. Transmissive direct-view displays are often built ontotransparent or glass substrates to facilitate a sandwich assemblyarrangement where one substrate, containing the light modulators, ispositioned directly on top of the backlight.

Each light modulator 102 includes a shutter 108 and an aperture 109. Toilluminate a pixel 106 in the image 104, the shutter 108 is positionedsuch that it allows light to pass through the aperture 109 towards aviewer. To keep a pixel 106 unlit, the shutter 108 is positioned suchthat it obstructs the passage of light through the aperture 109. Theaperture 109 is defined by an opening patterned through a reflective orlight-absorbing material in each light modulator 102.

The display apparatus also includes a control matrix connected to thesubstrate and to the light modulators for controlling the movement ofthe shutters. The control matrix includes a series of electricalinterconnects (e.g., interconnects 110, 112, and 114), including atleast one write-enable interconnect 110 (also referred to as a“scan-line interconnect”) per row of pixels, one data interconnect 112for each column of pixels, and one common interconnect 114 providing acommon voltage to all pixels, or at least to pixels from both multiplecolumns and multiples rows in the display apparatus 100. In response tothe application of an appropriate voltage (the “write-enabling voltage,V_(we)”), the write-enable interconnect 110 for a given row of pixelsprepares the pixels in the row to accept new shutter movementinstructions. The data interconnects 112 communicate the new movementinstructions in the form of data voltage pulses. The data voltage pulsesapplied to the data interconnects 112, in some implementations, directlycontribute to an electrostatic movement of the shutters. In otherimplementations, the data voltage pulses control switches, e.g.,transistors or other non-linear circuit elements that control theapplication of separate actuation voltages, which are typically higherin magnitude than the data voltages, to the light modulators 102. Theapplication of these actuation voltages then results in theelectrostatic driven movement of the shutters 108.

FIG. 2A is a perspective view of an illustrative shutter-based lightmodulator 200 suitable for incorporation into the direct-view MEMS-baseddisplay apparatus 100 of FIG. 1, according to an illustrative embodimentof the invention. The light modulator 200 includes a shutter 202 coupledto an actuator 204. The actuator 204 is formed from two separatecompliant electrode beam actuators 205 (the “actuators 205”), asdescribed in U.S. patent application Ser. No. 11/251,035, filed on Oct.14, 2005. The shutter 202 couples on one side to the actuators 205. Theactuators 205 move the shutter 202 transversely over a surface 203 in aplane of motion which is substantially parallel to the surface 203. Theopposite side of the shutter 202 couples to a spring 207 which providesa restoring force opposing the forces exerted by the actuator 204.

Each actuator 205 includes a compliant load beam 206 connecting theshutter 202 to a load anchor 208. The load anchors 208 along with thecompliant load beams 206 serve as mechanical supports, keeping theshutter 202 suspended proximate to the surface 203. The surface includesone or more aperture holes 211 for admitting the passage of light. Theload anchors 208 physically connect the compliant load beams 206 and theshutter 202 to the surface 203 and electrically connect the load beams206 to a bias voltage, in some instances, ground.

If the substrate is opaque, such as silicon, then aperture holes 211 areformed in the substrate by etching an array of holes through thesubstrate 204. If the substrate 204 is transparent, such as glass orplastic, then the first step of the processing sequence involvesdepositing a light blocking layer onto the substrate and etching thelight blocking layer into an array of holes 211. The aperture holes 211can be generally circular, elliptical, polygonal, serpentine, orirregular in shape.

Each actuator 205 also includes a compliant drive beam 216 positionedadjacent to each load beam 206. The drive beams 216 couple at one end toa drive beam anchor 218 shared between the drive beams 216. The otherend of each drive beam 216 is free to move. Each drive beam 216 iscurved such that it is closest to the load beam 206 near the free end ofthe drive beam 216 and the anchored end of the load beam 206.

In operation, a display apparatus incorporating the light modulator 200applies an electric potential to the drive beams 216 via the drive beamanchor 218. A second electric potential may be applied to the load beams206. The resulting potential difference between the drive beams 216 andthe load beams 206 pulls the free ends of the drive beams 216 towardsthe anchored ends of the load beams 206, and pulls the shutter ends ofthe load beams 206 toward the anchored ends of the drive beams 216,thereby driving the shutter 202 transversely towards the drive anchor218. The compliant members 206 act as springs, such that when thevoltage across the beams 206 and 216 potential is removed, the loadbeams 206 push the shutter 202 back into its initial position, releasingthe stress stored in the load beams 206.

A light modulator, such as light modulator 200, incorporates a passiverestoring force, such as a spring, for returning a shutter to its restposition after voltages have been removed. Other shutter assemblies, asdescribed in U.S. patent application Ser. Nos. 11/251,035 and11/326,696, incorporate a dual set of “open” and “closed” actuators anda separate sets of “open” and “closed” electrodes for moving the shutterinto either an open or a closed state.

U.S. patent application Ser. Nos. 11/251,035 and 11/326,696 havedescribed a variety of methods by which an array of shutters andapertures can be controlled via a control matrix to produce images, inmany cases moving images, with appropriate gray scale. In some casescontrol is accomplished by means of a passive matrix array of row andcolumn interconnects connected to driver circuits on the periphery ofthe display. In other cases it is appropriate to include switchingand/or data storage elements within each pixel of the array (theso-called active matrix) to improve either the speed, the gray scaleand/or the power dissipation performance of the display.

The control matrices described herein are not limited to controllingshutter-based MEMS light modulators, such as the light modulatorsdescribed above. For example, FIG. 2B is a cross-sectional view of arolling actuator-based light modulator 220 suitable for incorporationinto the direct-view MEMS-based display apparatus 100 of FIG. 1,according to an illustrative embodiment of the invention. As describedfurther in U.S. Pat. No. 5,233,459, entitled “Electric Display Device,”and U.S. Pat. No. 5,784,189, entitled “Spatial Light Modulator,” theentireties of which are incorporated herein by reference, a rollingactuator-based light modulator includes a moveable electrode disposedopposite a fixed electrode and biased to move in a preferred directionto produce a shutter upon application of an electric field. In oneembodiment, the light modulator 220 includes a planar electrode 226disposed between a substrate 228 and an insulating layer 224 and amoveable electrode 222 having a fixed end 230 attached to the insulatinglayer 224. In the absence of any applied voltage, a moveable end 232 ofthe moveable electrode 222 is free to roll towards the fixed end 230 toproduce a rolled state. Application of a voltage between the electrodes222 and 226 causes the moveable electrode 222 to unroll and lie flatagainst the insulating layer 224, whereby it acts as a shutter thatblocks light traveling through the substrate 228. The moveable electrode222 returns to the rolled state after the voltage is removed. The biastowards a rolled state may be achieved by manufacturing the moveableelectrode 222 to include an anisotropic stress state.

FIG. 2C is a cross-sectional view of a light-tap-based light modulator250 suitable for incorporation into the direct-view MEMS-based displayapparatus 100 of FIG. 1, according to an illustrative embodiment of theinvention. As described further in U.S. Pat. No. 5,771,321, entitled“Micromechanical Optical Switch and Flat Panel Display,” the entirety ofwhich is incorporated herein by reference, a light tap works accordingto a principle of frustrated total internal reflection. That is, light252 is introduced into a light guide 254, in which, withoutinterference, light 252 is for the most part unable to escape the lightguide 254 through its front or rear surfaces due to total internalreflection. The light tap 250 includes a tap element 256 that has asufficiently high index of refraction that, in response to the tapelement 256 contacting the light guide 254, light 252 impinging on thesurface of the light guide adjacent the tap element 256 escapes thelight guide 254 through the tap element 258 towards a viewer, therebycontributing to the formation of an image.

In one embodiment, the tap element 256 is formed as part of beam 258 offlexible, transparent material. Electrodes 260 coat portions one side ofthe beam 258. Opposing electrodes 260 are disposed on a cover plate 264positioned adjacent the layer 258 on the opposite side of the lightguide 254. By applying a voltage across the electrodes 260, the positionof the tap element 256 relative to the light guide 254 can be controlledto selectively extract light 252 from the light guide 254.

FIG. 2D is a cross sectional view of a third illustrativenon-shutter-based light modulator suitable for inclusion in variousembodiments of the invention Specifically, FIG. 2D is a cross sectionalview of an electrowetting-based light modulation array 270. The lightmodulation array 270 includes a plurality of electrowetting-based lightmodulation cells 272 a-272 d (generally “cells 272”) formed on anoptical cavity 274. The light modulation array 270 also includes a setof color filters 276 corresponding to the cells 272.

Each cell 272 includes a layer of water (or other transparent conductiveor polar fluid) 278, a layer of light absorbing oil 280, a transparentelectrode 282 (made, for example, from indium-tin oxide) and aninsulating layer 284 positioned between the layer of light absorbing oil280 and the transparent electrode 282. Illustrative implementation ofsuch cells are described further in U.S. Patent Application PublicationNo. 2005/0104804, published May 19, 2005 and entitled “Display Device.”In the embodiment described herein, the electrode takes up a portion ofa rear surface of a cell 272.

The remainder of the rear surface of a cell 272 is formed from areflective aperture layer 286 that forms the front surface of theoptical cavity 274. The reflective aperture layer 286 is formed from areflective material, such as a reflective metal or a stack of thin filmsforming a dielectric mirror. For each cell 272, an aperture is formed inthe reflective aperture layer 286 to allow light to pass through. Theelectrode 282 for the cell is deposited in the aperture and over thematerial forming the reflective aperture layer 286, separated by anotherdielectric layer.

The remainder of the optical cavity 274 includes a light guide 288positioned proximate the reflective aperture layer 286, and a secondreflective layer 290 on a side of the light guide 288 opposite thereflective aperture layer 286. A series of light redirectors 291 areformed on the rear surface of the light guide, proximate the secondreflective layer. The light redirectors 291 may be either diffuse orspecular reflectors. One of more light sources 292 inject light 294 intothe light guide 288.

In an alternative implementation, an additional transparent substrate ispositioned between the light guide 290 and the light modulation array270. In this implementation, the reflective aperture layer 286 is formedon the additional transparent substrate instead of on the surface of thelight guide 290.

In operation, application of a voltage to the electrode 282 of a cell(for example, cell 272 b or 272 c) causes the light absorbing oil 280 inthe cell to collect in one portion of the cell 272. As a result, thelight absorbing oil 280 no longer obstructs the passage of light throughthe aperture formed in the reflective aperture layer 286 (see, forexample, cells 272 b and 272 c). Light escaping the backlight at theaperture is then able to escape through the cell and through acorresponding color (for example, red, green, or blue) filter in the setof color filters 276 to form a color pixel in an image. When theelectrode 282 is grounded, the light absorbing oil 280 covers theaperture in the reflective aperture layer 286, absorbing any light 294attempting to pass through it.

The area under which oil 280 collects when a voltage is applied to thecell 272 constitutes wasted space in relation to forming an image. Thisarea cannot pass light through, whether a voltage is applied or not, andtherefore, without the inclusion of the reflective portions ofreflective apertures layer 286, would absorb light that otherwise couldbe used to contribute to the formation of an image. However, with theinclusion of the reflective aperture layer 286, this light, whichotherwise would have been absorbed, is reflected back into the lightguide 290 for future escape through a different aperture.

The roller-based light modulator 220, light tap 250, andelectrowetting-based light modulation array 270 are not the onlyexamples of a non-shutter-based MEMS modulator suitable for control bythe control matrices described herein. Other forms of non-shutter-basedMEMS modulators could likewise be controlled by various ones of thecontrol matrices described herein without departing from the scope ofthe invention.

FIG. 3A is a schematic diagram of a control matrix 300 suitable forcontrolling the light modulators incorporated into the direct-viewMEMS-based display apparatus 100 of FIG. 1, according to an illustrativeembodiment of the invention. FIG. 3B is a perspective view of an array320 of shutter-based light modulators connected to the control matrix300 of FIG. 3A, according to an illustrative embodiment of theinvention. The control matrix 300 may address an array of pixels 320(the “array 320”). Each pixel 301 includes an elastic shutter assembly302, such as the shutter assembly 200 of FIG. 2A, controlled by anactuator 303. Each pixel also includes an aperture layer 322 thatincludes aperture holes 324. Further electrical and mechanicaldescriptions of shutter assemblies such as shutter assembly 302, andvariations thereon, can be found in U.S. patent application Ser. Nos.11/251,035 and 11/326,696.

The control matrix 300 is fabricated as a diffused orthin-film-deposited electrical circuit on the surface of a substrate 304on which the shutter assemblies 302 are formed. The control matrix 300includes a scan-line interconnect 306 for each row of pixels 301 in thecontrol matrix 300 and a data-interconnect 308 for each column of pixels301 in the control matrix 300. Each scan-line interconnect 306electrically connects a write-enabling voltage source 307 to the pixels301 in a corresponding row of pixels 301. Each data interconnect 308electrically connects a data voltage source, (“Vd source”) 309 to thepixels 301 in a corresponding column of pixels 301. In control matrix300, the data voltage V_(d) provides the majority of the energynecessary for actuation of the shutter assemblies 302. Thus, the datavoltage source 309 also serves as an actuation voltage source.

Referring to FIGS. 3A and 3B, for each pixel 301 or for each shutterassembly in the array of pixels 320, the control matrix 300 includes atransistor 310 and a capacitor 312. The gate of each transistor 310 iselectrically connected to the scan-line interconnect 306 of the row inthe array 320 in which the pixel 301 is located. The source of eachtransistor 310 is electrically connected to its corresponding datainterconnect 308. The actuators 303 of each shutter assembly include twoelectrodes. The drain of each transistor 310 is electrically connectedin parallel to one electrode of the corresponding capacitor 312 and tothe one of the electrodes of the corresponding actuator 303. The otherelectrode of the capacitor 312 and the other electrode of the actuator303 in shutter assembly 302 are connected to a common or groundpotential.

In operation, to form an image, the control matrix 300 write-enableseach row in the array 320 in sequence by applying V_(we) to eachscan-line interconnect 306 in turn. For a write-enabled row, theapplication of V_(we) to the gates of the transistors 310 of the pixels301 in the row allows the flow of current through the data interconnects308 through the transistors to apply a potential to the actuator 303 ofthe shutter assembly 302. While the row is write-enabled, data voltagesV_(d) are selectively applied to the data interconnects 308. Inimplementations providing analog gray scale, the data voltage applied toeach data interconnect 308 is varied in relation to the desiredbrightness of the pixel 301 located at the intersection of thewrite-enabled scan-line interconnect 306 and the data interconnect 308.In implementations providing digital control schemes, the data voltageis selected to be either a relatively low magnitude voltage (i.e., avoltage near ground) or to meet or exceed V_(at) (the actuationthreshold voltage). In response to the application of V_(at) to a datainterconnect 308, the actuator 303 in the corresponding shutter assembly302 actuates, opening the shutter in that shutter assembly 302. Thevoltage applied to the data interconnect 308 remains stored in thecapacitor 312 of the pixel 301 even after the control matrix 300 ceasesto apply V_(we) to a row. It is not necessary, therefore, to wait andhold the voltage V_(we) on a row for times long enough for the shutterassembly 302 to actuate; such actuation can proceed after thewrite-enabling voltage has been removed from the row. The voltage in thecapacitors 312 in a row remain substantially stored until an entirevideo frame is written, and in some implementations until new data iswritten to the row.

The pixels 301 of the array 320 are formed on a substrate 304. The arrayincludes an aperture layer 322, disposed on the substrate, whichincludes a set of aperture holes 324 for each pixel 301 in the array320. The aperture holes 324 are aligned with the shutter assemblies 302in each pixel. In one implementation the substrate 304 is made of atransparent material, such as glass or plastic. In anotherimplementation the substrate 304 is made of an opaque material, but inwhich holes are etched to form the aperture holes 324.

The shutter assembly 302 together with the actuator 303 can be madebi-stable. That is, the shutters can exist in at least two equilibriumpositions (e.g. open or closed) with little or no power required to holdthem in either position. More particularly, the shutter assembly 302 canbe mechanically bi-stable. Once the shutter of the shutter assembly 302is set in position, no electrical energy or holding voltage is requiredto maintain that position. The mechanical stresses on the physicalelements of the shutter assembly 302 can hold the shutter in place.

The shutter assembly 302 together with the actuator 303 can also be madeelectrically bi-stable. In an electrically bi-stable shutter assembly,there exists a range of voltages below the actuation voltage of theshutter assembly, which if applied to a closed actuator (with theshutter being either open or closed), hold the actuator closed and theshutter in position, even if an opposing force is exerted on theshutter. The opposing force may be exerted by a spring such as spring207 in shutter-based light modulator 200, or the opposing force may beexerted by an opposing actuator, such as an “open” or “closed” actuator.

The light modulator array 320 is depicted as having a single MEMS lightmodulator per pixel. Other embodiments are possible in which multipleMEMS light modulators are provided in each pixel, thereby providing thepossibility of more than just binary “on’ or “off” optical states ineach pixel. Certain forms of coded area division gray scale are possiblewherein the multiple MEMS light modulators in the pixel are provided,and where with aperture holes 324 associated with each of the lightmodulators have unequal areas.

FIG. 3D is yet another suitable control matrix 340 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 340 controls an array of pixels 342 thatinclude shutter assemblies 344. The control matrix 340 includes a singledata interconnect 348 for each column of pixels 342 in the controlmatrix. The actuators in the shutter assemblies 344 can be made eitherelectrically bi-stable or mechanically bi-stable.

The control matrix 340 includes a scan-line interconnect 346 for eachrow of pixels 342 in the control matrix 340. The control matrix 340further includes a charge interconnect 350, and a global actuationinterconnect 354, and a shutter common interconnect 355. Theseinterconnects 350, 354 and 355 are shared among pixels 342 in multiplerows and multiple columns in the array. In one implementation, theinterconnects 350, 354, and 355 are shared among all pixels 342 in thecontrol matrix 340. Each pixel 342 in the control matrix includes ashutter charge transistor 356, a shutter discharge transistor 358, ashutter write-enable transistor 357, and a data store capacitor 359.Control matrix 340 also incorporates an optional voltage stabilizingcapacitor 352 which is connected in parallel with the source and drainof discharge switch transistor 358. The gate terminals of the chargingtransistor 356 are connected directly to the charge interconnect 350,along with the drain terminal of the charging transistor 356. Inoperation, the charging transistors 356 operate essentially as diodes,they can pass a current in only one direction.

At the beginning of each frame addressing cycle the control matrix 340applies a voltage pulse to the charge interconnect 350, allowing currentto flow through charging transistor 356 and into the shutter assemblies344 of the pixels 342. After this charging pulse, each of the shutterelectrodes of shutter assemblies 344 will be in the same voltage state.After the voltage pulse, the potential of charge interconnect 350 isreset to zero, and the charging transistors 356 will prevent the chargestored in the shutter assemblies 344 from being dissipated throughcharge interconnect 350. The charge interconnect 350, in oneimplementation, transmits a pulsed voltage equal to or greater thanV_(at), e.g., 40V. In one implementation the imposition of a voltage inexcess of V_(at) of causes all of the shutter assemblies connected tothe charging interconnect 350 to actuate or move into the same state,for instance the shutter closed state.

Each row is then write-enabled in sequence. The control matrix 340applies a write-enabling voltage V_(we) to the scan-line interconnect346 corresponding to each row. While a particular row of pixels 342 iswrite-enabled, the control matrix 340 applies a data voltage to the datainterconnect 348 corresponding to each column of pixels 342 in thecontrol matrix 340. The application of V_(we) to the scan-lineinterconnect 346 for the write-enabled row turns on the write-enabletransistor 357 of the pixels 342 in the corresponding scan line. Thevoltages applied to the data interconnect 348 is thereby caused to bestored on the data store capacitor 359 of the respective pixels 342.

In control matrix 340 the global actuation interconnect 354 is connectedto the source of the shutter discharge switch transistor 358.Maintaining the global actuation interconnect 354 at a potentialsignificantly above that of the shutter common interconnect 355 preventsthe turn-on of the discharge switch transistor 358, regardless of whatcharge is stored on the capacitor 359. Global actuation in controlmatrix 340 is achieved by bringing the potential on the global actuationinterconnect 354 to ground or to substantially the same potential as theshutter common interconnect 355, enabling the discharge switchtransistor 358 to turn-on in accordance to the whether a data voltagehas been stored on capacitor 359. During the global actuation step, forthe pixels wherein a data voltage has been stored on capacitor 359, thedischarge transistor turns on, charge drainsout of the actuators ofshutter assembly 344, and the shutter assembly 344 is allowed to move oractuate into its relaxed state, for instance the shutter open state. Forpixels wherein no data voltage was stored on the capacitor 359, thedischarge transistor 358 do not turn on and the shutter assembly 344remains charged. For those pixels a voltage remains across the actuatorsof shutter assemblies 344 and those pixels remain, for instance, in theshutter closed state. During the global actuation step all pixelsconnected to the same global actuation interconnect, and with datastored on capacitor 359, move into their new states at substantially atthe same time. Control matrix 340 does not depend on electricalbi-stability in the shutter assembly 344 in order to achieve globalactuation.

Applying partial voltages to the data store capacitor 359 allows partialturn-on of the discharge switch transistor 358 during the time that theglobal actuation interconnect 354 is brought to its actuation potential.In this fashion, an analog voltage is created on the shutter assembly344, for providing analog gray scale.

In some implementation the global actuation interconnect 354 isconnected to every shutter discharge transistor 358 in every row andcolumn in the array of pixels. In other implementations the globalactuation interconnect 354 is connected to the shutter dischargetransistors within only a sub-group of pixels in multiple rows andcolumns. As will be discussed with reference to FIGS. 18 and 19, thearray of pixels can be arranged in banks, where each bank of pixels isconnected by means of a global actuation interconnects to a uniqueglobal actuation driver. In this implementation the control circuit canload data into the selected banks and then actuate only the selectedbank globally by means of the selected global actuation driver. In oneimplementation, the display is separated into two banks, with one set ofglobal drivers and global actuation interconnects connected to pixels inthe odd-numbered rows while a separate set of global drivers and globalactuation interconnects is connected to pixels in the even-numberedrows. In other implementations as many as 6 or 8 separately actuatableaddressing banks are employed. Other implementations of circuits forcontrolling displays are described in U.S. Ser. No. 11/607,715 filedDec. 1, 2006 and entitled “Circuits for Controlling Display Apparatus,”which is incorporated herein by reference.

FIG. 3C illustrates a portion of a direct view display 380 that includesthe array of light modulators 320 depicted in FIG. 3B disposed on top ofbacklight 330. In one implementation the backlight 330 is made of atransparent material, i.e. glass or plastic, and functions as a lightguide for evenly distributing light from lamps 382, 384, and 386throughout the display plane. When assembling the display 380 as a fieldsequential display, the lamps 382, 384, and 386 can be alternate colorlamps, e.g. red, green, and blue lamps respectively.

A number of different types of lamps 382-386 can be employed in thedisplays, including without limitation: incandescent lamps, fluorescentlamps, lasers, or light emitting diodes (LEDs). Further, lamp 382-386 ofdirect view display 380 can be combined into a single assemblycontaining multiple lamps. For instance a combination of red, green, andblue LEDs can be combined with or substituted for a white LED in a smallsemiconductor chip, or assembled into a small multi-lamp package.Similarly each lamp can represent an assembly of 4-color LEDs, forinstance a combination of red, yellow, green, and blue LEDs.

The shutter assemblies 302 function as light modulators. By use ofelectrical signals from the associated control matrix the shutterassemblies 302 can be set into either an open or a closed state. Onlythe open shutters allow light from the lightguide 330 to pass through tothe viewer, thereby forming a direct view image.

In direct view display 380 the light modulators are formed on thesurface of substrate 304 that faces away from the light guide 330 andtoward the viewer. In other implementations the substrate 304 can bereversed, such that the light modulators are formed on a surface thatfaces toward the light guide. In these implementations it is sometimespreferable to form an aperture layer, such as aperture layer 322,directly onto the top surface of the light guide 330. In otherimplementations it is useful to interpose a separate piece of glass orplastic between the light guide and the light modulators, such separatepiece of glass or plastic containing an aperture layer, such as aperturelayer 322 and associated aperture holes, such as aperture holes 324. Itis preferable that the spacing between the plane of the shutterassemblies 302 and the aperture layer 322 be kept as close as possible,preferably less than 10 microns, in some cases as close as 1 micron.Descriptions of other optical assemblies useful for this invention canbe found in US Patent Application Publication No. 20060187528A1 filedSep. 2, 2005 and entitled “Methods and Apparatus for Spatial LightModulation” and in U.S. Ser. No. 11/528,191 filed Sep. 26, 2006 andentitled “Display Apparatus with Improved Optical Cavities,” which areboth incorporated herein by reference.

In some displays, color pixels are generated by illuminating groups oflight modulators corresponding to different colors, for example, redgreen and blue. Each light modulator in the group has a correspondingfilter to achieve the desired color. The filters, however, absorb agreat deal of light, in some cases as much as 60% of the light passingthrough the filters, thereby limiting the efficiency and brightness ofthe display. In addition, the use of multiple light modulators per pixeldecreases the amount of space on the display that can be used tocontribute to a displayed image, further limiting the brightness andefficiency of such a display.

The human brain, in response to viewing rapidly changing images, forexample, at frequencies of greater than 20 Hz, averages images togetherto perceive an image which is the combination of the images displayedwithin a corresponding period. This phenomenon can be utilized todisplay color images while using only single light modulators for eachpixel of a display, using a technique referred to in the art as fieldsequential color. The use of field sequential color techniques indisplays eliminates the need for color filters and multiple lightmodulators per pixel. In a field sequential color enabled display, animage frame to be displayed is divided into a number of sub-frameimages, each corresponding to a particular color component (for example,red, green, or blue) of the original image frame. For each sub-frameimage, the light modulators of a display are set into statescorresponding to the color component's contribution to the image. Thelight modulators then are illuminated by a lamp of the correspondingcolor. The sub-images are displayed in sequence at a frequency (forexample, greater than 60 Hz) sufficient for the brain to perceive theseries of sub-frame images as a single image. The data used to generatethe sub-frames are often fractured in various memory components. Forexample, in some displays, data for a given row of display are kept in ashift-register dedicated to that row. Image data is shifted in and outof each shift register to a light modulator in a corresponding column inthat row of the display according to a fixed clock cycle.

FIG. 4 is a timing diagram 400 corresponding to a display process fordisplaying images using field sequential color, which can be implementedaccording to an illustrative embodiment of the invention, for example,by a MEMS direct-view display described in FIG. 7. The timing diagramsincluded herein, including the timing diagram 400 of FIG. 4, conform tothe following conventions. The top portions of the timing diagramsillustrate light modulator addressing events. The bottom portionsillustrate lamp illumination events.

The addressing portions depict addressing events by diagonal linesspaced apart in time. Each diagonal line corresponds to a series ofindividual data loading events during which data is loaded into each rowof an array of light modulators, one row at a time. Depending on thecontrol matrix used to address and drive the modulators included in thedisplay, each loading event may require a waiting period to allow thelight modulators in a given row to actuate. In some implementations, allrows in the array of light modulators are addressed prior to actuationof any of the light modulators. Upon completion of loading data into thelast row of the array of light modulators, all light modulators areactuated substantially simultaneously. One method for such actuation isdescribed further in relation to FIG. 11.

Lamp illumination events are illustrated by pulse trains correspondingto each color of lamp included in the display. Each pulse indicates thatthe lamp of the corresponding color is illuminated, thereby displayingthe sub-frame image loaded into the array of light modulators in theimmediately preceding addressing event.

The time at which the first addressing event in the display of a givenimage frame begins is labeled on each timing diagram as AT0. In most ofthe timing diagrams, this time falls shortly after the detection of avoltage pulse vsync, which precedes the beginning of each video framereceived by a display. The times at which each subsequent addressingevent takes place are labeled as AT1, AT2, . . . AT(n−1), where n is thenumber of sub-frame images used to display the image frame. In some ofthe timing diagrams, the diagonal lines are further labeled to indicatethe data being loaded into the array of light modulators. For example,in the timing diagrams of FIGS. 4 and 5, D0 represents the first dataloaded into the array of light modulators for a frame and D(n−1)represents the last data loaded into the array of light modulators forthe frame. In the timing diagrams of FIGS. 10, 12-17 and 19, the dataloaded during each addressing event corresponds to a bitplane.

As described in further detail in relation to FIGS. 6A-6C, a bitplane isa coherent set of data identifying desired modulator states formodulators in multiple rows and multiple columns of an array of lightmodulators. Moreover, each bitplane corresponds to one of a series ofsub-frame images derived according to a binary coding scheme. That is,each sub-frame image for a color component of an image frame is weightedaccording to a binary series 1, 2, 4, 8, 16, etc. The bitplane with thelowest weighting is referred to as the least significant bitplane and islabeled in the timing diagrams and referred to herein by the firstletter of the corresponding color component followed by the number 0.For each next-most significant bitplane for the color components, thenumber following the first letter of the color component increases byone. For example, for an image frame broken into 4 bitplanes per color,the least significant red bitplane is labeled and referred to as the R0bitplane. The next most significant red bitplane is labeled and referredto as R1, and the most significant red bitplane is labeled and referredto as R3.

Lamp-related events are labeled as LT0, LT1, LT2 . . . LT(n−1). Thelamp-related event times labeled in a timing diagram, depending on thetiming diagram, either represent times at which a lamp is illuminated ortimes at which a lamp is extinguished. The meaning of the lamp times ina particular timing diagram can be determined by comparing theirposition in time relative to the pulse trains in the illuminationportion of the particular timing diagram. Specifically referring back tothe timing diagram 400 of FIG. 4, to display an image frame according tothe timing diagram 400, a single sub-frame image is used to display eachof three color components of an image frame. First, data, D0, indicatingmodulator states desired for a red sub-frame image are loaded into anarray of light modulators beginning at time AT0. After addressing iscomplete, the red lamp is illuminated at time LT0, thereby displayingthe red sub-frame image. Data, D1, indicating modulator statescorresponding to a green sub-frame image are loaded into the array oflight modulators at time AT1. A green lamp is illuminated at time LT1.Finally, data, D2, indicating modulator states corresponding to a bluesub-frame image are loaded into the array of light modulators and a bluelamp is illuminated at times AT2 and LT2, respectively. The process thenrepeats for subsequent image frames to be displayed.

The level of gray scale achievable by a display that forms imagesaccording to the timing diagram of FIG. 4 depends on how finely thestate of each light modulator can be controlled. For example, if thelight modulators are binary in nature, i.e., they can only be on or off,the display will be limited to generating 8 different colors. The levelof gray scale can be increased for such a display by providing lightmodulators than can be driven into additional intermediate states. Insome embodiments related to the field sequential technique of FIG. 4,MEMS light modulators can be provided which exhibit an analog responseto applied voltage. The number of grayscale levels achievable in such adisplay is limited only by the resolution of digital to analogconverters which are supplied in conjunction with data voltage sources,such as voltage source 309.

Alternatively, finer grayscale can be generated if the time period usedto display each sub-frame image is split into multiple time periods,each having its own corresponding sub-frame image. For example, withbinary light modulators, a display that forms two sub-frame images ofequal length and light intensity per color component can generate 27different colors instead of 8. Gray scale techniques that break eachcolor component of an image frame into multiple sub-frame images arereferred to, generally, as time division gray scale techniques.

FIG. 5 is a timing diagram corresponding to a display process fordisplaying an image frame by displaying multiple equally weightedsub-frame images per color that can be implemented by variousembodiments of the invention. In the timing diagram of FIG. 5, eachcolor component of an image frame is divided into four equally weightedsub-frame images. More particularly, each sub-frame image for a givencolor component is illuminated for the same amount of time at the samelamp intensity. Thus, the number portion of the data identifier (e.g.,R0, R1, or G3) only refers to the order in which the correspondingsub-frame image is displayed, and not to any weighting value. Assumingthe light modulators are binary in nature, a display utilizing thisgrayscale technique can generate 5 gray scale levels per color or 125distinct colors.

More specifically, first, data, R0, indicating modulator states desiredfor a first red sub-frame image are loaded into an array of lightmodulators beginning at time AT0. After the light modulators haveachieved the states indicated by data R0, the red lamp is illuminated,thereby displaying the first red sub-frame image. The red lamp isextinguished at time AT1, which is when data, R1, indicating modulatorstates corresponding to the next red sub-frame image are loaded into thearray of light modulators. The same steps repeat for each red sub-frameimage corresponding to data R1, R2 and R3. The steps as described forthe red sub-frame images R0-R3 then repeat for the green sub-frameimages G0-G3, and then for the blue sub-frame images B0-B3. The processthen repeats for subsequent image frames to be displayed. The addressingtimes in FIG. 5 can be established through a variety of methods. Sincethe data is loaded at regular intervals, and since the sub-frame imagesare illuminated for equal times, a fixed clock cycle running with afrequency 12 times that of the vsync frequency can be sufficient forcoordinating the display process.

By contrast to the timing diagram shown in FIG. 5, which employsequal-weighting for each of 4 sub-frame images per color, other displayprocesses made possible by this invention employ unequal illuminationweightings between sub-frame images. Such unequal weightings enable acoded time division gray scale technique wherein much larger numbers ofgray scale levels can be displayed with the same number of sub-frameimages. Display processes using coded time division gray scale, in somecases, utilizes bitplanes to implement a binary weighting scheme ofsub-frame images. FIGS. 6A-6C depict a process for generating abitplane, according to an illustrative embodiment of the invention. FIG.6A is a schematic diagram of a digital image signal 600 received by adisplay device. The image signal 600 encodes data corresponding to imageframes. For a given image frame encoded in the image signal 600, theimage signal 600 includes a series of bits for each pixel included inthe image frame. The data is encoded in a pixel-by-pixel fashion. Thatis, the image signal includes all data for the color of a single pixelin the image frame before it includes data for the next pixel.

For example, in FIG. 6A, the data for an image frame begins with a vsyncsignal indicating the beginning of the image frame. The image signal 600then includes, for example, 24 bits indicating the color of the pixel inthe first row of the first column of the image frame. Of the 24 bits, 8encode a red component of the pixel, 8 encode a green component, and 8encode a blue component of the pixel. Each set of eight bits is referredto as a coded word. An eight bit coded word for each color enables adescription of 256 unique brightness levels for each color, or 16million unique combinations of the colors red, green, and blue. Withinthe coded word, each of the 8 bits represents a particular position orplace value (also referred to as a significance value) in the codedword. In FIG. 6A, these place values are indicated by a coding schemesuch as R0, R1, R2, R3, etc. R0 represents the least significant bit forthe color red. R7 represents the most significant bit for the color red.G7 is the most significant bit for the color green, and B7 is the mostsignificant bit for the color blue. Quantitatively, in binary coding,the place values corresponding to R0, R1, R2, . . . R7 are given by thebinary series 2⁰, 2¹, 2², . . . 2⁷. In other examples, the image signal600 may include more or fewer bits per color component of an image. Forexample, the image signal 600 may include 3, 4, 5, 6, 7, 9, 10, 11, 12or more bits per color component of an image frame.

The data as received in image signal 600 is organized by rows andcolumns. Generally the image signal provides all of the data for pixelsin the first row before proceeding to subsequent rows. Within the firstrow, all of the data is received for the pixel in the first columnbefore it is received for pixels in succeeding columns of the same row.

FIG. 6B is a schematic diagram of a memory buffer 620 useful forconverting a received image signal into a bitplane, according to anillustrative embodiment of the invention. As described above, a bitplaneincludes data for pixels in multiple columns and multiple rows of adisplay corresponding to a single significance value of a grayscalecoded word for a color component of an image frame. To convert a binarycoded image signal, such as image signal 600 of FIG. 6A, into bitplanes,bits having the significance level are grouped together into a singledata structure. A small memory buffer 620 is employed to organizeincoming image data. The memory buffer 620 is organized in an array ofrows and columns, and allows for data to be read in and out in byaddressing either individual rows or by addressing individual columns.

Incoming data, which, as described above, is received in a pixel bypixel format, is read into the memory buffer 620 in successive rows. Thememory buffer 620 stores data relevant to only a single designated rowof the display, i.e. it operates on only a fraction of the incoming dataat any given time. Each numbered row within the memory buffer 620contains complete pixel data for a given column for the designated row.Each row of the memory buffer 620 contains complete gray scale data fora given pixel.

Once the small memory buffer 620 has been loaded with data for allcolumns of a given row of the display, the data in the memory buffer 620can be read out to populate a bitplane data structure. The data is readout column by column. Each column includes a single place value of thegray scale code word of the pixels row of the display. These valuescorrespond to desired states of light modulators in the display. Forexample, a 0 may refer to an “open” light modulator state and 1 mayrefer to a “closed” light modulator state, or visa versa. This processrepeats for multiple rows in the display.

FIG. 6C is a schematic diagram of portions of two bitplanes 650 and 660,according to an illustrative embodiment of the invention. The firstbitplane 650 includes data corresponding to the least significant bitsof the gray scale coded words identifying the level of red (i.e., R0values) for the first 10 columns and 15 rows of pixels of a display. Thesecond bitplane 660 includes data corresponding to the second-leastsignificant bits of the gray scale coded words identifying the level ofred (i.e., R1) for the same 10 columns and 15 rows of pixels of thedisplay.

Alternative weighting schemes are available within the method of codedtime division gray scale. Binary coding is appropriate where the spatiallight modulators allow only two states, e.g. open or closed or e.g. onor off. A ternary weighting system is also a possibility. For instance aspatial light modulator and associated control matrix could allow forthree unique states of light transmission or reflection. These could beclosed, ½ open, and full open. MEMS-based modulators could, forinstance, be constructed where the ½ open and full open states resultfrom the application of distinct actuation voltages. Alternatively, the½ open state could be achieved through the actuation of only one out oftwo equal-area MEMS modulators which are supplied in each pixel.

A sub-frame data set will refer herein to the general case of datastructures which are not necessarily bitplanes: namely data structuresthat store information about the desired states of modulators inmultiple rows and multiple columns of the array. For the case of ternarycoding a single sub-frame data set would include a ternary number valuefor each of the pixels in multiple rows and columns, e.g. a 0, 1, or 2.Sequential sub-frame images according to a ternary coding scheme wouldbe weighted according to the base-3 numbering system, with weights inthe series 1,3,9,27, etc. Compared to a binary coding system, a ternarycoding system makes possible even greater numbers of achievable grayscale levels when displayed using an equal number of sub-frame images.By extension, as MEMS pixels or modulators are developed capable of 4 or5 unique modulation states at each pixel, the use of quaternary orbase-5 coding systems become advantageous in the control system.

FIG. 7 is a block diagram of a direct-view display 700, according to anillustrative embodiment of the invention. The direct-view display 700includes an array of light modulators 702, a controller 704, a set oflamps 706, and driver sets 708, 710, 714, and 716. The array of lightmodulators 702 includes lights modulators arranged in rows and columns.Suitable light modulators include, without limitation, any of theMEMS-based light modulators described above in relation to FIGS. 2A-2D.In one implementation, the array of light modulators 702 takes the formof the array of light modulators 320 depicted in FIG. 3B. The lightmodulators are be controlled by a control matrix, such as the controlmatrices described in FIGS. 3A and 3D.

In general, the controller receives an image signal 717 from an externalsource and generates outputs data and control signals to the drivers708, 710, 714, and 716 to control the light modulators in the array oflight modulators 702 and the lamps 706. The order in which the data andcontrol signals are output is referred to herein as an “outputsequence,” described further below More particularly, the controller 704includes an input processing module 718, a memory control module 720, aframe buffer 722, a timing control module 724, and a schedule tablestore 726.

A module may be implemented as a hardware circuit including applicationspecific integrated circuits, custom VLSI circuits or gate arrays,off-the-shelf semiconductors such as logic chips, memories, transistors,or other discrete components. A module may also be implemented inprogrammable hardware devices such as field programmable gate arrays,programmable array logic, programmable logic devices or the like.

Modules may also be implemented in software for execution by varioustypes of processors. An identified module of executable code may, forinstance, include one or more physical or logical blocks of computerinstructions which may, for instance, be organized as an object,procedure, or function. Nevertheless, the executables of an identifiedmodule need not be physically located together, but may includedisparate instructions stored in different locations which, when joinedlogically together, make up the module and achieve the stated purposefor the module.

Indeed, a module of executable code could be a single instruction, ormany instructions, and may even be distributed over several differentcode segments, among different programs, and across several memorydevices. Similarly, operational data may be identified and illustratedherein within modules, and may be embodied in any suitable form andorganized within any suitable type of data structure. The operationaldata may be collected as a single data set, or may be distributed overdifferent locations including over different storage devices, and mayexist, at least partially, merely as electronic signals on a system ornetwork.

The illustration of direct view display 700 in FIG. 7 portrays thecontroller 704 and drivers 708, 710, 714, and 716 as separate functionalblocks. These blocks are understood to represent distinguishablecircuits and/or modules of executable code. In some implementations theblocks 704, 708, 710, 714, and 716 may be provided as distinct chips orcircuits which are connected together by means of circuit boards and/orcables. In other implementations, several of these blocks can bedesigned together into a single semiconductor chip such that theirboundaries are nearly indistinguishable except by function. In someimplementations the storage area referred to as frame buffer 722 isprovided as a functional area within a custom design of the controllercircuit 704. In other implementations the frame buffer 722 isrepresented by a separate off-the-shelf memory chip such as a DRAM orSRAM.

The input processing module 718 receives the image signal 717 andprocesses the data encoded therein into a format suitable for displayingvia the array of light modulators 702. The input processing module 718takes the data encoding each image frame and converts it into a seriesof sub-frame data sets. A sub-frame data set includes information aboutthe desired states of modulators in multiple rows and multiple columnsof the array of light modulators 702 aggregated into a coherent datastructure. The number and content of sub-frame data sets used to displayan image frame depends on the grayscale technique employed by thecontroller 704. For example, the sub-frame data sets needed to form animage frame using a coded time-division gray scale technique differsfrom the number and content of sub-frame data sets used to display animage frame using a non-coded time division gray scale technique. Whilein various embodiments, the image processing module 718 may convert theimage signal 717 into non-coded sub-frame data sets, ternary codedsub-frame data sets, or other form of coded sub-frame data set,preferably, the image processing module 718 converts the image signal717 into bitplanes, as described above in relation to FIGS. 6A-6C.

In addition to and in many cases prior to deriving the sub-frame datasets, the input processing module can carry out a number of otheroptional processing tasks. It may re-format or interpolate incomingdata. For instance, it may rescale incoming data horizontally,vertically, or both, to fit within the spatial-resolution limits ofmodulator array 702. It may also convert incoming data from aninterlaced format to a progressive scan format. It may also resample theincoming data in time to reduce frame rates while maintaining acceptableflicker within the characteristics of MEMS display 700. It may performadjustments to contrast gradations of the incoming data, in some casesreferred to as gamma corrections, to better match the gammacharacteristics and/or contrast precision available in the MEMS display700. It may alter the grayscale levels assigned between neighboringpixels (spatial dithering) and/or assigned between succeeding imageframes (temporal dithering) to enhance the gray scale precisionavailable in the display. And it may perform adjustments to color valuesexpressed in the pixel data. In one instance of color adjustment, thedata is transformed to match the color coordinates of the lamps 706 usedin display 700. For embodiments where four or more distinct-color lampsare employed, the input processing module will transform the data froman incoming 3-color space and map it to coordinates appropriate to the4-color space.

The input processing module 718 outputs the sub-frame data sets to thememory control module 720. The memory control module 720 then stores thesub-frame data sets in the frame buffer 722. The frame buffer ispreferably a random access memory, although other types of serial memorycan be used without departing from the scope of the invention. Thememory control module 720, in one implementation, stores the sub-framedata set in a predetermined memory location based on the color andsignificance in a coding scheme of the sub-frame data set. In otherimplementations, the memory control module 720 stores the sub-frame dataset in a dynamically determined memory location and stores that locationin a lookup table for later identification. In one particularimplementation, the frame buffer 722 is configured for the storage ofbitplanes.

The memory control module 720 is also responsible for, upon instructionfrom the timing control module 724, retrieving sub-image data sets fromthe frame buffer 722 and outputting them to the data drivers 708. Thedata drivers 708 load the data output from the memory control module 720into the light modulators of the array of light modulators 702. Thememory control module 720 outputs the data in the sub-image data setsone row at a time. In one implementation, the frame buffer 722 includestwo buffers, whose roles alternate. While the memory control module 720stores newly generated bitplanes corresponding to a new image frame inone buffer, it extracts bitplanes corresponding to the previouslyreceived image frame from the other buffer for output to the array oflight modulators 702. Both buffer memories can reside within the samecircuit, separated only by address.

The timing control module 724 manages the output by the controller 704of data and command signals according to an output sequence. The outputsequence includes the order and timing with which sub-frame data setsare output to the array of light modulators 702 and the timing andcharacter of illumination events. The output sequence, in someimplementations, also includes global actuation events. At least some ofthe parameters that define the output sequence are stored in volatilememory. This volatile memory is referred to as schedule table store 726.A table including the data stored in the schedule table store 726 isreferred to herein as a “schedule table” or alternately as a “sequencetable”. The data stored therein need not actually be stored in tableformat. Conceptually, the data stored in the schedule table store 726 iseasier for a human to understand if displayed in table format. Theactual data structure used to store output sequence data can be, forexample a series of bit strings. Each string of bits includes a seriesof coded words corresponding to timing values, memory, addresses, andillumination data. An illustrative data structure for storing outputsequence parameters is described further in relation to FIG. 24. Otherdata structures may be employed without departing from the scope of theinvention.

Some output sequence parameters may be stored as hardwired logic in thetiming control module 724. For example, the logic incorporated into thetiming control module to wait until a particular event time may beexpressed as follows:

mycount <= mycount + 1; if mycount = 1324 then triggersignal <= ‘1’;else triggersignal <= ‘0’;This logic employs a counter which increments at every clock cycle. Whenthe clock counter reaches the timing value 1324 a trigger signal issent. For example, the trigger signal may be sent to the memory controlmodule 720 to initiate the loading of a bitplane into the modulators.Or, the trigger signal could be sent to lamp driver 706 to switch thelamp on or off. In the example above, the logic takes the form of logiccircuitry built directly into the timing control module 724. Theparticular timing parameter 1324 is a scalar value contained within thecommand sequence. In another implementation of timing control module724, the logic does not include a specific value for a number of clockpulses to wait, but refers instead to one of a series of timing valueswhich are stored in schedule stable store 726.

The output sequence parameters stored in the schedule table store 726vary in different embodiments of the invention. In one embodiment, theschedule table store 726 stores timing values associated with eachsub-frame data set. For example, the schedule table store 726 may storetiming values associated with the beginning of each addressing event inthe output sequence, as well as timing values associated with lampillumination and/or lamp extinguishing events. In other embodiments, theschedule table store 726 stores lamp intensity values instead of or inaddition to timing values associated with addressing events. In variousembodiments, the schedule table store 726 stores an identifierindicating where each sub-image data set is stored in the frame buffer722, and illumination data indicating the color or colors associatedwith each respective sub-image data set.

The nature of the timing values stored in the schedule table store 726can vary depending on the specific implementation of the controller 704.The timing value, as stored in the schedule table store 726, in oneimplementation, is a number of clock cycles, which for example, havepassed since the initiation of the display of an image frame, or sincethe last addressing or lamp event was triggered. Alternatively, thetiming value may be an actual time value, stored in microseconds ormilliseconds.

Table 1 is an illustrative schedule table illustrating parameterssuitable for storage in the schedule table store 726 for use by thetiming control module 724. Several additional illustrative scheduletables are described in further detail in relation to FIGS. 13, 14A-B,15-17 and 19.

TABLE 1 Schedule Table 1 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R R R R G G G - - - B Blamp time LT0 LT1 LT2 LT3 LT4 LT5 LT6 - - - LT(n − 1) LTn

The Table 1 schedule table includes two timing values for each sub-framedata set, an addressing time and a lamp illumination time. Theaddressing times AT0-AT(n−1) are associated with times at which thememory control module 720 outputs a respective sub-frame data set, inthis case a bitplane, to the array of light modulators 702. The lampillumination times LT0-LT(n−1) are associated with times at whichcorresponding lamps are illuminated. In fact, each time value in theschedule table may trigger more than one event. For example, in somegrayscale techniques, lamp activity is synchronized with the actuationof the light modulators to avoid illuminating the light modulators whilethey are not in an addressed state. Thus, in some implementations, theaddressing times AT, not only trigger addressing events, they alsotrigger lamp extinguishing events. Similarly, in other implementations,lamp extinguishing events also trigger addressing events.

The address data, labeled in the table as “memory location of sub-framedata set,” in the schedule table can be stored in a number of forms. Forexample, in one implementation, the address is a specific memorylocation in the frame buffer of the beginning of the correspondingbitplane, referenced by buffer, column, and row numbers. In anotherimplementation, the address stored in the schedule table store 726 is anidentifier for use in conjunction with a look up table maintained by thememory control module 720. For example, the identifier may have a simple6-bit binary “xxxxxx” word structure where the first 2 bits identify thecolor associated with the bitplane, while the next 4 bits refer to thesignificance of the bitplane. The actual memory location of the bitplaneis then stored in a lookup table maintained by the memory control module720 when the memory control module 720 stores the bitplane into theframe buffer. In other implementations the memory locations forbitplanes in the output sequence may be stored as hardwired logic withinthe timing control module 724.

The timing control module 724 may retrieve schedule table entries usingseveral different methods. In one implementation the order of entries inthe schedule table is fixed; the timing control module 724 retrieveseach entry in order until reaching a special entry that designates theend of the sequence. Alternatively, a sequence table entry may containcodes that direct the timing control module 724 to retrieve an entrywhich may be different from the next entry in the table. Theseadditional fields may incorporate the ability to perform jumps,branches, and looping in analogy with the control features of a standardmicroprocessor instruction set. Such flow control modifications to theoperation of the timing control module 724 allow a reduction in the sizeof the sequence table.

The direct-view display 700 also includes a programming link 730. Theprogramming link 730 provides a means by which the schedule table store726 may be modified by external circuits or computers. In otherembodiments the programming link connects directly to a system processorwithin the same housing as the direct view display 700. The systemprocessor may be programmed to alter the schedule table store inaccordance with the type of image or data to be displayed by display700. The external processor, using the programming link 730, can modifythe parameters stored in the schedule table store 726 to alter theoutput sequence used by the controller 704. For example, the programminglink 730 can be used to change the timing parameters stored in theschedule table store 726 to accommodate different frame rates. Thetiming parameters associated with each bitplane and the number ofbitplanes displayed can be modified by the programming link 730 toadjust the number of colors or grayscale the display can provide.Average brightness can be adjusted by changing lamp intensity values.Color saturation can be modified by the programming link by alteringpercentage of brightness formed using a white color field or byadjusting color mixing (described further in relation to FIG. 17).

The direct-view display includes a set of lamps 706 for illuminating thearray of light modulators 702. In one implementation, the direct-viewdisplay 700 includes a red lamp, a green lamp, and a blue lamp. Inanother implementation, the direct-view display 700 also includes awhite lamp. In still another implementation, the direct-view display 700includes multiple lamps for each color spaced along a side of the arrayof light modulators 702.

In addition to the red, green, blue, white color combination, other lampcombinations are possible which expand the space or gamut of achievablecolors. A useful 4-color lamp combination with expanded color gamut isred, blue, true green (about 520 nm) plus parrot green (about 550 nm).Another 5-color combination which expands the color gamut is red, green,blue, cyan, and yellow. A 5-color analogue to the well known YIQ colorspace can be established with the lamps white, orange, blue, purple, andgreen. A 5-color analog to the well known YUV color space can beestablished with the lamps white, blue, yellow, red, and cyan.

Other lamp combinations are possible. For instance, a useful 6-colorspace can be established with the lamp colors red, green, blue, cyan,magenta, and yellow. A 6-color space can also be established with thecolors white, cyan, magenta, yellow, orange, and green. A large numberof other 4-color and 5-color combinations can be derived from amongstthe colors already listed above. Further combinations of 6, 7, 8 or 9lamps with different colors can be produced from the colors listedabove, Additional colors may be employed using lamps with spectra whichlie in between the colors listed above.

The direct-view display 700 also includes a number of sets of drivercircuits 708, 710, 714, and 716 controlled by, and in electricalcommunication with the various components of the controller 704. Thedirect-view display 700 includes a set of scan drivers 708 forwrite-enabling each of the rows of the array of light modulators insequence. The scan drivers 708 are controlled by, and in electricalcommunication with the timing control module 724. Data drivers 710 arein electrical communication with the memory control 720. The direct-viewdisplay 700 may include one driver circuit 710 for each column in thearray of light modulators 702, or it may have some smaller number ofdata drivers 710, each responsible for loading data into multiplecolumns of the array of light modulators 702.

The direct-view display 700 includes a series of common drivers 714,including global actuation drivers, actuation voltage drivers, and, insome embodiments, additional common voltage drivers. Common drivers 714are in electrical communication with the timing control module 720 andlight modulators in multiple rows and multiple columns of the array oflight modulators 702.

The lamps 706 are driven by lamp drivers 716. The lamps may be inelectrical communication both with the memory control module 720 and/orthe timing control module 724. The timing control module 724 controlsthe timing of the illumination of the lamps 706. Illumination intensityinformation may also be supplied by the timing control module 724, or itmay be supplied by the memory control module 720.

Some electronic devices employing displays according to this inventionemploy variations on the design of controller 704. For such displays thecontroller does not include an input processing module or a framebuffer. Instead the system processor attached to the electronic deviceprovides a pre-formatted output sequence of bitplanes for display by thecontroller, drivers, and the array of MEMS light modulators. In such adisplay the timing control module coordinates the output of bitplanedata for the array of modulators and controls the illumination of lampsassociated with each bitplanes. The timing control module may makereference to a schedule table store, within which are stored timingvalues for addressing and lamp events and/or lamp intensities associatedwith each of the bitplanes.

FIG. 8 is a flow chart of a method of displaying video 800 (the “displaymethod 800”) suitable for use by a direct-view display such as thedirect-view display 700 of FIG. 7, according to an illustrativeembodiment of the invention. Referring to FIGS. 7 and 8, the displaymethod 800 begins with the provision of an array of light modulators(step 801), such as the array of light modulators 702. Then, the displaymethod 800 proceeds with two interrelated processes, which operate inparallel. The first process is referred to herein as an image processingprocess 802 of the display method 800. The second process is referred toas a display process 804.

The image processing process 802 begins with the receipt of an imagesignal (step 806) by the video input 718. As described above, the imagesignal encodes one or more image frames for display on the direct-viewdisplay 700. In one embodiment, the image signal is received asindicated in FIG. 6A. That is, data for each pixel is receivedsequentially, pixel-by-pixel, row-by-row. The data for a given pixelincludes one or more bits for each color component of the pixel.

Upon receipt of data for an image frame (step 806), the controller 704of the direct-view display 700 derives a plurality of sub-frame datasets for the image frame (step 808). Preferably, the image processingmodule 718 of the controller 704 derives a plurality of bitplanes basedon the data in the image signal 717 as described above in relation toFIGS. 6A-6C. The imaging process continues at step 810, wherein thesub-frame data sets are stored in the memory. Preferably the biplanesare stored in frame buffer 722, according to address information thatallows them to be randomly accessed at a later points in the process.

The display process 804 begins with the initiation of the display of animage frame (step 812), for example, in response to the detection of avsync pulse in the input signal 717. Then, the first sub-frame data setcorresponding to the image frame is output by the memory control module720 (step 814) to the array of light modulators 702 in an addressingevent. The memory address of this first sub-frame data set is determinedbased on data in the schedule table store 726. Preferably, the sub-framedata set is a bitplane. After the modulators addressed in the firstsub-frame data set achieve the state indicated in the sub-frame dataset, the lamp or lamps corresponding to the sub-frame data set loadedinto the light modulators is illuminated (step 816). The time at whichthe light is illuminated may be governed by a timing value stored in theschedule table store 726 associated with sub-frame image. The lampremains illuminated until the next time the light modulators in thearray of light modulators begin to change state, at which time the lampis extinguished. The extinguishing time, too, may be determined based ona time value stored in the schedule table store 726. Depending on theaddressing technique implemented by the controller 704, theextinguishing time may be before or after the next addressing eventbegins.

After the array of light modulators is illuminated, but not necessarilybefore or at the same time the lamp is extinguished, the controller 704determines, based on the output sequence, whether the recently displayedsub-frame image is the last sub-frame image to be displayed for theimage frame (decision block 818). If it is not the last sub-frame image,the next sub-frame data set is loaded into the array of light modulators702 in another addressing event (step 814). If the recently displayedsub-frame image is the last sub-frame image of an image frame, thecontroller 704 awaits initiation of the display of a subsequent displayinitiation event (step 812).

FIG. 9 is a more detailed flow chart of an illustrative display process900 suitable for use as part of the display method 800 for displayingimages on the direct-view display 700. In the display process 900, thesub-frame data sets employed by the direct-view display are bitplanes.The display process 900 begins with the initiation of the display of animage frame (step 902). For example, the display of an image frame maybe initiated (step 902) in response to the detection by the controller704 of a vsync pulse in the image signal 717. Next, the bitplanecorresponding to the image frame is output by the controller 704 to thearray of light modulators 702 (step 904). Each row of the sub-frame dataset is loaded sequentially. As each row is addressed, the controller 704waits a sufficient amount of time to ensure the light modulators in therespective row actuate before beginning to address the next row in thearray of light modulators 702. During this time, as states of the lightmodulators in the array of light modulators 702 are in flux, the lampsof the direct-view display 700 remain off.

After waiting a sufficient amount of time to ensure all rows of thearray of light modulators 702 have actuated according to the data in thebitplane, the color lamp 702 corresponding to the bitplane isilluminated (step 906), thereby displaying the sub-frame imagecorresponding to the bitplane loaded into the array of light modulators702. In one implementation, this waiting time is stored in the scheduletable store 726. In other implementations, this waiting time is a fixedvalue hardwired into the timing control modue 724 as a number of clockcycles following the beginning of an addressing event.

The controller then waits a time stored in the schedule table data store726 associated with the sub-frame image before extinguishing the lamp(step 908). At decision block 910, the controller 704 determines whetherthe most recently displayed sub-frame image is the last sub-frame imageof the image frame being displayed. If the most recently displayedsub-frame image is the last sub-frame image for the image frame, thecontroller awaits the initiation of the display of a subsequent imageframe (step 902). If it is not the last sub-frame image for the imageframe, the controller 704 begins loading the next bitplane (step 904)into the array of light modulators 702. This addressing event may betriggered directly by the extinguishing of the lamp at step 908, or itmay begin after a time associated with a timing value stored in theschedule table store 726 passes.

FIG. 10 is a timing diagram 1000 that corresponds to an implementationof the display process 900 that utilizes an output sequence having asparameters the values stored in the Table 1 schedule table. The timingdiagram 1000 corresponds to a coded-time division grayscale displayprocess in which image frames are displayed by displaying four sub-frameimages for each of three color components (red, green, and blue) of theimage frame. Each sub-frame image displayed of a given color isdisplayed at the same intensity for half as long a time period as theprior sub-frame image, thereby implementing a binary weighting schemefor the sub-frame images.

The display of an image frame begins upon the detection of a vsyncpulse. As indicated on the timing diagram and in the Table 1 scheduletable, the first sub-frame data set R3, stored beginning at memorylocation M0, is loaded into the array of light modulators 702 in anaddressing event that begins at time AT0. According to the Table 1schedule table, the red lamp is then illuminated at time LT0. LT0 isselected such that it occurs after each of the rows in the array oflight modulators 702 has been addressed, and the light modulatorsincluded therein have actuated. At time AT1, the controller 704 of thedirect-view display both extinguishes the red lamp and begins loadingthe subsequent bitplane, R2, into the array of light modulators 702.According to the Table 1 schedule table, this bitplane is storedbeginning at memory location M1. The process repeats until all bitplanesidentified in the Table 1 schedule table have been displayed. Forexample, at time AT4, the controller 704 extinguishes the red lamp andbegins loading the most significant green bitplane, G3, into the arrayof light modulators 702. Similarly at time LT6, the controller 704 turnson the green lamp until time AT7, at which it time it is extinguishedagain.

The time period between vsync pulses in the timing diagram is indicatedby the symbol FT, indicating a frame time. In some implementations theaddressing times AT0, AT1, etc. as well as the lamp times LT0, LT1, etc.are designed to accomplish 4 sub-frame images per color within a frametime FT of 16.6 milliseconds, i.e. according to a frame rate of 60 Hz.In other implementations the time values stored in schedule table store726 can be altered to accomplish 4 sub-frame images per color within aframe time FT of 33.3 milliseconds, i.e. according to a frame rate of 30Hz. In other implementations frame rates as low as 24 Hz may be employedor frame rates in excess of 100 Hz may be employed.

In the particular implementation of coded time division gray scaleillustrated by timing diagram 1000, the controller outputs 4 sub-frameimages to the array 702 of light modulators for each color to bedisplayed. The illumination of each of the 4 sub-frame images isweighted according to the binary series 1,2,4,8. The display process intiming diagram 1000, therefore, displays a 4-digit binary word for grayscale in each color, that is, it is capable of displaying 16 distinctgray scale levels for each color, despite the loading of only 4sub-images per color. Through combinations of the colors, theimplementation of timing diagram 1000 is capable of displaying more than4000 distinct colors.

In other implementations of display process 800 the sub-frame images inthe sequence of sub-frame images need not be weighted according to thebinary series 1,2,4,8, etc. As mentioned above, the use of base-3weighting can be useful as a means of expressing sub-frame data setsderived from a ternary coding scheme. Still other implementations employa mixed coding scheme. For instance the sub-frame images associated withthe least significant bits may be derived and illuminated according to abinary weighting scheme, while the sub-frame images associated with themost significant bits may be derived and illuminated with a more linearweighting scheme. Such a mixed coding helps to reduce the largedifferences in illumination periods for the most significant bits and ishelpful in reducing image artifacts such as dynamic false contouring.

FIG. 11 is a more detailed flow chart of an illustrative display process1100 suitable for use as part of the display method 800 for displayingimages on the direct-view display 700. As in the display process 900,the display process 1100 utilizes bitplanes for sub-frame data sets. Incontrast to display process 900, however, display process 1100 includesa global actuation functionality. In a display utilizing globalactuation, pixels in multiple rows and multiple columns of the displayare addressed before any of the actuators actuate. In the displayprocess 1100, all rows of the display are addressed prior to actuation.Thus, while in display process 900, a controller must wait a certainamount of time after loading data into each row of light modulators toallow sufficient time for the light modulators to actuate, in displayprocess 1100, the controller need only wait this “actuation time” once,after all rows have been addressed. One control matrix capable ofproviding a global actuation functionality is described above inrelation to FIG. 3D.

Display process 1100 begins with the initiation of the display of a newimage frame (step 1102). Such an initiation may be triggered by thedetection of a vsync voltage pulse in the image signal 717. Then, at atime stored in the schedule table store 726 after the initiation of thedisplay process for the image frame, the controller 704 begins loadingthe first bitplane into the light modulators of the array of lightmodulators 702 (step 1104).

At step 1106, any lamp currently illuminated is extinguished. Step 1106may occur at or before the loading of a particular bitplane (step 1104)is completed, depending on the significance of the bitplane. Forexample, in some embodiments, to maintain the binary weighting ofbitplanes with respect to one another, some bitplanes may need to beilluminated for a time period that is less than the amount of time ittakes to load the next bitplane into the array of light modulators 702.Thus, a lamp illuminating such a bitplane is extinguished while the nextbitplane is being loaded into the array of light modulators (step 1104).To ensure that lamps are extinguished at the appropriate time, in oneembodiment, a timing value is stored in the schedule table store 726 toindicate the appropriate light extinguishing time.

When the controller 704 has completed loading a given bitplane into thearray of light modulators 702 (step 1104) and extinguished anyilluminated lamps (step 1106), the controller 704 issues a globalactuation command (step 1108) to a global actuation driver, causing allof the light modulators in the array of light modulators 702 to actuateat substantially the same time. Global actuation drivers represent atype of common driver 714 included as part of display 700. The globalactuation drivers may connect to modulators in the array of lightmodulators, for instance, by means of global actuation interconnectssuch as interconnect 354 of control matrix 340.

In some implementations the step 1108, globally actuate, includes aseries of steps or commands issued by the timing control module 724. Forinstance, in certain control matrices described in co-pending U.S. Ser.No. 11/607,715, the global actuation step may involve a (first) chargingof shutter mechanisms by means of a charging interconnect, followed by a(second) driving of a shutter common interconnect toward groundpotential (at which point all commonly connected light modulators moveinto their closed state), followed after a constant waiting period forshutter actuation, followed by a (third) grounding of the globalactuation interconnect (at which point only selected shutters move intotheir designated open states). Each of the charging interconnects,shutter common interconnects, and global actuation interconnects isconnected to a separate driver circuit, responsive to trigger signalssent at the appropriate times according to timing values stored in thetiming control module 724.

After waiting the actuation time of the light modulators, the controller704 issues an illumination command (step 1110) to the lamp drivers toturn on the lamp corresponding to the recently loaded bitplane. Theactuation time is the same for each bitplane loaded, and thus need notbe stored in the schedule table store 726. It can be permanently storedin the timing control module 724 in hardware, firmware, or software.

After the lamp corresponding to the bitplane is illuminated (step 1110),at decision block 1112, the controller 704 determines, based on theoutput sequence, whether the currently loaded bitplane is the lastbitplane for the image frame to be displayed. If so, the controller 704awaits initiation of the display of the next image frame (step 1102).Otherwise, the controller 704 begins loading the next bitplane into thearray of light modulators 702.

FIG. 12 is a timing diagram 1200 that corresponds to an implementationof the display process 1100 that utilizes an output sequence having asparameters the values stored in the Table 1 schedule table. While thedisplay processes corresponding to FIGS. 10 and 12 utilize similarstored parameters, their operation is quite different. Similar to thedisplay process corresponding to timing diagram 1000 of FIG. 10, thedisplay process corresponding to timing diagram 1200 uses a coded-timedivision grayscale addressing process in which image frames aredisplayed by displaying four sub-frame images for each of three colorcomponents (red, green, and blue) of the image frame. Each sub-frameimage displayed of a given color is displayed at the same intensity forhalf as long a time period as the prior sub-frame image, therebyimplementing a binary weighting scheme for the sub-frame images.However, the display process corresponding to timing diagram 1200differs from the timing diagram 1000 in that it incorporates the globalactuation functionality described in the display process 1100. As such,the lamps in the display are illuminated for a significantly greaterportion of the frame time. The display can therefore either displaybrighter images, or it can operate its lamps at lower power levels whilemaintaining the same brightness level. As brightness and powerconsumption are not linearly related, the lower illumination leveloperating mode, while providing equivalent image brightness, consumesless energy.

More specifically, the display of an image frame in timing diagram 1200begins upon the detection of a vsync pulse. As indicated on the timingdiagram and in the Table 1 schedule table, the bitplane R3, storedbeginning at memory location M0, is loaded into the array of lightmodulators 702 in an addressing event that begins at time AT0. Once thecontroller 704 outputs the last row of data for a bitplane to the arrayof light modulators 702, the controller 704 outputs a global actuationcommand. After waiting the actuation time, the controller 704 causes thered lamp to be illuminated. As indicated above, since the actuation timeis a constant for all sub-frame images, no corresponding time valueneeds to be stored in the schedule table store 726 to determine thistime. At time AT1, the controller 704 begins loading the subsequentbitplane R2, which, according to the schedule table, is stored beginningat memory location M1, into the array of light modulators 702.

Lamp extinguishing event times LT0-LT11 occur at times stored in theschedule table store 726. The times may be stored in terms of clockcycles following the detection of a vsync pulse, or they may be storedin terms of clock cycles following the beginning of the loading of theprevious bitplane into the array of light modulators 702. For bitplaneswhich are to be illuminated for a period longer than the time it takesto load a bitplane into the array of light modulators 726, the lampextinguishing times are set in the schedule table to coincide with thecompletion of an addressing event corresponding to the subsequentsub-frame image. For example, LT0 is set to occur at a time after AT0which coincides with the completion of the loading of bitplane R2. LT1is set to occur at a time after AT1 which coincides with the completionof the loading of bitplane R1.

Some bitplanes, such as R0, G0, and B0, however, are intended to beilluminated for a period of time that is less than the amount of time ittakes to load a bitplane into the array. Thus, LT3, LT7, and LT11 occurin the middle of subsequent addressing events.

In alternate implementations the sequence of lamp illumination and dataaddressing can be reversed. For instance the addressing of bitplanescorresponding to the subsequent sub-frame image can follow immediatelyupon the completion of a global actuation event, while the illuminationof a lamp can be delayed until a lamp illumination event at some pointafter the addressing has begun.

FIG. 13 is a timing diagram 1300 that corresponds to anotherimplementation of the display process 1100 that utilizes a table similarto Table 2 as a schedule table. The timing diagram 1300 corresponds to acoded-intensity grayscale addressing process similar to that describedwith respect to FIG. 5 in that each sub-frame image for a given colorcomponent (red, green, and blue) is illuminated for the same amount oftime. However, in contrast to the display process depicted in FIG. 5, inthe display process corresponding to timing diagram 1300, each sub-frameimage of a particular color component is illuminated at half theintensity as the prior sub-frame image of the color component, therebyimplementing a binary weighting scheme without varying lamp illuminationtimes.

TABLE 2 Schedule Table 2 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R R R R G G G - - - B Blamp intensity IL0 IL1 IL2 IL3 IL4 IL5 IL6 - - - IT(n − 1) ITn

More specifically, the display of an image frame in timing diagram 1300begins upon the detection of a vsync pulse. As indicated on the timingdiagram and in the Table 2 schedule table, the bitplane R3, storedbeginning at memory location M0, is loaded into the array of lightmodulators 702 in an addressing event that begins at time AT0. Once thecontroller 704 outputs the last row data of a bitplane to the array oflight modulators 702, the controller 704 outputs a global actuationcommand. After waiting the actuation time, the controller causes the redlamp to be illuminated at a lamp intensity IL0 stored in the Table 2schedule table. Similar to the addressing process described with respectto FIG. 12, since the actuation time is a constant for all sub-frameimages, no corresponding time value needs to be stored in the scheduletable store 726 to determine this time. At time AT1, the controller 704begins loading the subsequent bitplane R2, which, according to theschedule table, is stored beginning at memory location M1, into thearray of light modulators 702. The sub-frame image corresponding tobitplane R2 is illuminated at an intensity level IL1, as indicated inTable 2, which is equal to half of the intensity level IL0. Similarly,the intensity level IL2 for bitplane R1 is equal to half of theintensity level IL1, and the intensity level Il3 for bitplane R0 isequal to half of the intensity level IL2.

For each sub-frame image, the controller 704 may extinguish theilluminating lamp at the completion of an addressing event correspondingto the next sub-frame image. As such, no corresponding time value needsto be stored in the schedule table store 726 corresponding to lampillumination times.

FIG. 14A is a timing diagram 1400 that corresponds to anotherimplementation of the display process 1100 that utilizes a table similarto Table 3 as a schedule table. The timing diagram 1400 corresponds to acoded-time division grayscale addressing process in which image framesare displayed by displaying five sub-frame images for each of threecolor components (red, green, and blue) of the image frame. By includingan extra sub-frame image per color component, the display processcorresponding to timing diagram 1400 can display twice the number ofgray scale levels at each color as the display process that correspondsto timing diagram 1200. Each sub-frame image displayed of a given coloris displayed at the same intensity for half as long a time period as theprior sub-frame image, thereby implementing a binary pulse widthweighting scheme for the sub-frame images.

TABLE 3 Schedule Table 3 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R R R R R G G - - - B Blamp time LT0 LT1 LT2 LT3 LT4 LT5 LT6 - - - LT(n − 1) LTn

More specifically, the display of an image frame in timing diagram 1200begins upon the detection of a vsync pulse. As indicated on the timingdiagram, the bitplane R4, stored beginning at memory location M0, isloaded into the array of light modulators 702 in an addressing eventthat begins at time AT0. Once the controller 704 outputs the last rowdata of a bitplane to the array of light modulators 702, the controller704 outputs a global actuation command. After waiting the actuationtime, the controller causes the red lamp to be illuminated. Similar tothe addressing process described with respect to FIG. 12, since theactuation time is a constant for all sub-frame images, no correspondingtime value needs to be stored in the schedule table store 726 todetermine this time. At time AT1, the controller 704 begins loading thesubsequent bitplane R3, which is stored beginning at memory location M1,into the array of light modulators 702.

Lamp extinguishing event times occur at times stored in the scheduletable store 726. The times may be stored in terms of clock cyclesfollowing the detection of a vsync pulse, or they may be stored in termsof clock cycles following the beginning of the loading of the previousbitplane into the array of light modulators 702. For bitplanes which areto be illuminated for a period longer than the time it takes to load abitplane into the array of light modulators 726, the lamp extinguishingtimes are set in the schedule table to coincide with the completion ofan addressing event corresponding to the subsequent sub-frame image. Forexample, LT0 is set to occur at a time after AT0 which coincides withthe completion of the loading of bitplane R3. LT1 is set to occur at atime after AT1 which coincides with the completion of the loading ofbitplane R2.

Similar to the addressing process corresponding to the timing diagram1200 of FIG. 12, some bitplanes, such as R1 and R0, G1 and G0, and B1and B0 are intended to be illuminated for a period of time that is lessthan the amount of time it takes to load a bitplane into the array.Thus, their corresponding lamp extinguishing times occur in the middleof subsequent addressing events. Because the lamp extinguishing timesdepend on whether the corresponding illumination times are less than orgreater than the time required for addressing, the correspondingschedule table includes lamp times, e.g., LT0, LT1, LT2, etc.

FIG. 14B is a timing diagram 1450 that corresponds to anotherimplementation of the display process 1100 that utilizes the parametersstored in Table 4 as a schedule table. The timing diagram 1450corresponds to a coded-time division and intensity grayscale addressingprocess similar to that of the timing diagram 1400, except that theweighting of the least significant sub-image and the second leastsignificant sub-image are achieved by varying lamp intensity in additionto lamp illumination time. In particular, sub-frame images correspondingto the least significant bitplane and the second least significantbitplane are illuminated for the same length of time as the sub-frameimages corresponding to the third least significant bitplane, but at onequarter and one half the intensity, respectively. By combining intensitygrayscale with time division grayscale, all the bitplanes may beilluminated for a period of time equal to or longer than the time ittakes to load a bitplane into the array of light modulators 702. Thiseliminates the need for lamp extinguishing times to be stored in theschedule table store 726.

TABLE 4 Schedule Table 4 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R R R R R G G - - - B Blamp intensity IL0 IL1 IL2 IT3 IT4 IT5 IT6 - - - IT(n − 1) ITn

More specifically, the display of an image frame in timing diagram 1450begins upon the detection of a vsync pulse. As indicated on the timingdiagram and schedule table 4, the bitplane R4, stored beginning atmemory location M0, is loaded into the array of light modulators 702 inan addressing event that begins at time AT0. Once the controller 704outputs the last row of data of a bitplane to the array of lightmodulators 702, the controller 704 outputs a global actuation command.After waiting the actuation time, the controller causes the red lamp tobe illuminated at a lamp intensity IL0 stored in the schedule tablestore 726. Similar to the addressing process described with respect toFIG. 12, since the actuation time is a constant for all sub-frameimages, no corresponding time value needs to be stored in the scheduletable store 726 to determine this time. At time AT1, the controller 704begins loading the subsequent bitplane R3, which, according to theschedule table, is stored beginning at memory location M1, into thearray of light modulators 702. The sub-frame image corresponding tobitplane R3 is illuminated at an intensity level IL1, as indicated inTable 2, which is equal to the intensity level IL0. Similarly, theintensity level IL2 for bitplane R2 is equal to the intensity level IL1.However, the intensity level IT3 for bitplane R1 is half that of theintensity level IL2, and the intensity level IT4 for bitplane R0 is halfthat of the intensity level IT3. Similar to the display processdescribed with respect to FIG. 13, for each sub-frame image, thecontroller 704 may extinguish the illuminating lamp at the completion ofan addressing event corresponding to the next sub-frame image. As such,no corresponding time value needs to be stored in the schedule tablestore 726 to determine this time.

The timing diagram 1450 corresponds to a display process in whichperceived brightness of sub-images of an output sequence are controlledin a hybrid fashion. For some sub-frame images in the output sequence,brightness is controlled by modifying the period of illumination of thesub-frame image. For other sub-frame images in the output sequence,brightness is controlled by modifying illumination intensity. It isuseful in a direct view display to provide the capability forcontrolling both pulse widths and intensities independently. In oneimplementation of such independent control, the lamp drivers 714 areresponsive to variable intensity commands issued from the timing controlmodule 724 as well as to timing or trigger signals from the timingcontrol module 724 for the illumination and extinguishing of the lamps.For independent pulse width and intensity control, the schedule tablestore 726 stores parameters that describe the required intensity oflamps in addition to the timing values associated with theirillumination.

It is useful to define an illumination value as the product (or theintegral) of an illumination period (or pulse width) with the intensityof that illumination. For a given time interval assigned in an outputsequence for the illumination of a bitplane there are numerousalternative methods for controlling the lamps to achieve any requiredillumination value. Three such alternate pulse profiles for lampsappropriate to this invention are compared in FIG. 14C. In FIG. 14C thetime markers 1482 and 1484 determine time limits within which a lamppulse must express its illumination value. In a global actuation schemefor driving MEMS-based displays, the time marker 1482 might representthe end of one global actuation cycle, wherein the modulator states areset for a bitplane previously loaded, while the time marker 1484 canrepresent the beginning of a subsequent global actuation cycle, forsetting the modulator states appropriate to the subsequent bitplane. Forbitplanes with smaller significance, the time interval between themarkers 1482 and 1484 can be constrained by the time necessary to loaddata subsets, e.g. bitplanes, into the array of modulators. Theavailable time interval, in these cases, is substantially longer thatthe time required for illumination of the bitplane, assuming a simplescaling from the pulse widths assigned to bits of larger significance.

The lamp pulse 1486 is a pulse appropriate to the expression of aparticular illumination value. The pulse width 1486 completely fills thetime available between the markers 1482 and 1484. The intensity oramplitude of lamp pulse 1486 is adjusted, however, to achieve a requiredillumination value. An amplitude modulation scheme according to lamppulse 1486 is useful, particularly in cases where lamp efficiencies arenot linear and power efficiencies can be improved by reducing the peakintensities required of the lamps.

The lamp pulse 1488 is a pulse appropriate to the expression of the sameillumination value as in lamp pulse 1486. The illumination value ofpulse 1488 is expressed by means of pulse width modulation instead of byamplitude modulation. As shown in the timing diagram 1400, for manybitplanes the appropriate pulse width will be less than the timeavailable as determined by the addressing of the bitplanes.

The series of lamp pulses 1490 represent another method of expressingthe same illumination value as in lamp pulse 1486. A series of pulsescan express an illumination value through control of both the pulsewidth and the frequency of the pulses. The illumination value can beconsidered as the product of the pulse amplitude, the available timeperiod between markers 1482 and 1484, and the pulse duty cycle.

The lamp driver circuitry can be programmed to produce any of the abovealternate lamp pulses 1486, 1488, or 1490. For example, the lamp drivercircuitry can be programmed to accept a coded word for lamp intensityfrom the timing control module 724 and build a sequence of pulsesappropriate to intensity. The intensity can be varied as a function ofeither pulse amplitude or pulse duty cycle.

FIG. 15 is a timing diagram 1500 that corresponds to anotherimplementation of the display process 1100 that utilizes a scheduletable similar to Table 5. The timing diagram 1500 corresponds to acoded-time division grayscale addressing process similar to thatdescribed with respect to FIG. 12, except that restrictions have beenplaced on illumination periods for the most significant bits and ruleshave been established for the ordering of the bitplanes in the displaysequence. The sequencing rules illustrated for timing diagram 1500 areestablished to help reduce two visual artifacts which detract from imagequality in field sequential displays, i.e. color breakup and flicker.Color breakup is reduced by increasing the frequency of color changes,that is by alternating between sub-images of different colors at afrequency preferably in excess of 180 Hz. Flicker is reduced in itssimplest manifestation by ensuring that frame rates are substantiallygreater than 30 Hz, that is, by ensuring that bitplanes of similarsignificance which appear in subsequent image frames are separated bytime periods of less than 25 milliseconds.

TABLE 5 Schedule Table 5 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R G B R R G G - - - G B

Sequencing rules associated with color breakup and flicker can beimplemented by the technique of bit splitting. In particular, in timingdiagram 1500, the most significant bits, e.g. R3, G3, and B3, are splitin two, that is: reduced to half of their nominal illumination periodand then repeated or displayed twice within the time of any given imageframe. The red bitplane R3 for instance, is first loaded to themodulation array at time event AT0 and is then loaded for the secondtime at the time event AT9. The illumination period associated with themost significant bitplane R3, loaded at time event AT9, is equal to theillumination period associated with bitplane R2, which is loaded at thetime event AT12. Because the most significant bitplane R3 appears twicewithin the image frame, however, the illumination value associated withthe information contained within bitplane R3 is still twice thatallotted to the next most significant bitplane R2.

In addition, instead of displaying sub-frame images of an image groupedby color, as shown in the timing diagrams 1000, 1200, 1300, 1400 and1450, the timing diagram 1500 displays sub-frame images corresponding toa given color interspersed among sub-frame images corresponding to othercolors. For example, to display an image according to the timing diagram1500, a display first loads and displays the first occurrence of themost significant bitplane for red, R3, followed immediately by the mostsignificant green bitplane, G3, followed immediately by the mostsignificant blue bitplane B3. Since the most significant bitplanes havebeen split, these color changes occur fairly rapidly, with the longesttime periods between color changes about equal to the illumination timeof the next most significant bitplane, R2. The time periods betweenillumination of sub-frame images of different colors, illustrated as thetime period J in timing diagram 1500, are preferably held to less than 4milliseconds, more preferably less than 2.8 milliseconds. The smallerbitplanes, R1 and R0, G1 and G0, and B1 and B0, can still be groupedtogether, since the total of their illumination times is still less than4 milliseconds.

Interspersing or alternating between bitplanes or different colors helpsto reduce the imaging artifact of color breakup. It is preferable toavoid grouping the output of bitplanes by color. For instance, althoughthe bitplane B3 is the third of the bitplanes to be output by thecontroller (at addressing event AT2), the appearance of the bluebitplane B3 does not imply the end of all possible appearances of redbitplanes within the frame time. Indeed the bitplane R1 for the colorred immediately follows B3 in the sequence of timing diagram 1500. It ispreferable to alternate between bitplanes of different color with thehighest frequency possible within an image frame.

To reduce the power associated with refreshing a display it is notalways possible to establish a frame rate in excess of 30 Hz. Alternaterules related to the ordering of the bitplanes may still be applied,however, to minimize flicker in the perceived image. In timing diagram1500 the time periods K and L represent the separation in time betweenevents in which the most significant bitplane in red, i.e. the mostsignificant bitplane R3 is output to the display. Similar time periods Kand L exist between successive occurrences of the other most significantbitplanes G3 and B3. The time period K represents the maximum timebetween output of most significant bitplanes within a given image frame.The time period L represents the maximum time between output of mostsignificant bitplanes in two consecutive image frames. In timing diagram1500 the sum of K+L is equal to the frame time, and for this embodiment,the frame time may be as long as 33 milliseconds (corresponding to a 30Hz frame rate). Flicker may still be reduced in displays wherebit-splitting is employed, if both time intervals K and L are held toless than 25 milliseconds, preferably less than 17 milliseconds.

Flicker may arise from a variety of factors wherein characteristics of adisplay are repeated at frequencies as low as 30 Hz. In timing diagram1500, for instance, the lesser significance bitplanes R1 and R0 areilluminate only once per frame, and the frame rate is as long as 30 Hz.Therefore images associated with these lesser bitplanes may contributeto the perception of flicker. The bank-wise addressing method describedwith respect to FIG. 19, however, will provide another mechanism bywhich even lesser bitplanes can be repeated at frequencies substantiallygreater than the frame rate.

Flicker may also be generated by the characteristic of bitplane jitter.Jitter appears when the spacing between similar bitplanes is not equalin the sequence of displayed bitplanes. Flicker would ensue, forinstance, if the time periods K and L between MSB red bitplanes were notequal. Flicker can be reduced by ensuring that time periods K and L areequal to within 10%. That is the length of time between a first time thebitplane corresponding to the most significant sub-frame image of acolor component of the image frame is output and a second time thebitplane corresponding to the most significant sub-frame image of thecolor component is output is within 10% of the length of time betweenthe second time the bitplane corresponding to the most significantsub-frame image of the color component is output and a subsequent timeat which a sub-frame image corresponding to the most significantsub-frame image of the color component is output.

FIG. 16 is a timing diagram 1600 that corresponds to anotherimplementation of the display process 1100 that utilizes the parameterslisted in Table 6. The timing diagram 1600 corresponds to a coded-timedivision grayscale addressing process in which image frames aredisplayed by displaying four sub-frame images for each color componentof the image frame. Each sub-frame image displayed of a given color isdisplayed at the same intensity for half as long a time period as theprior sub-frame image, thereby implementing a binary weighting schemefor the sub-frame images. The timing diagram 1600 is similar to thetiming diagram 1200 of FIG. 12, but has sub-frame images correspondingto the color white, in addition to the colors red, green and blue, thatare illuminated using a white lamp. The addition of a white lamp allowsthe display to display brighter images or operate its lamps at lowerpower levels while maintaining the same brightness level. As brightnessand power consumption are not linearly related, the lower illuminationlevel operating mode, while providing equivalent image brightness,consumes less energy. In addition, white lamps are often more efficient,i.e. they consume less power than lamps of other colors to achieve thesame brightness.

More specifically, the display of an image frame in timing diagram 1600begins upon the detection of a vsync pulse. As indicated on the timingdiagram and in the Table 6 schedule table, the bitplane R3, storedbeginning at memory location M0, is loaded into the array of lightmodulators 702 in an addressing event that begins at time AT0. Once thecontroller 704 outputs the last row data of a bitplane to the array oflight modulators 702, the controller 704 outputs a global actuationcommand. After waiting the actuation time, the controller causes the redlamp to be illuminated. Similar to the addressing process described withrespect to FIG. 12, since the actuation time is a constant for allsub-frame images, no corresponding time value needs to be stored in theschedule table store 726 to determine this time. At time AT4, thecontroller 704 begins loading the first of the green bitplanes, G3,which, according to the schedule table, is stored beginning at memorylocation M4. At time ATB, the controller 704 begins loading the first ofthe blue bitplanes, B3, which, according to the schedule table, isstored beginning at memory location M8. At time AT12, the controller 704begins loading the first of the white bitplanes, W3, which, according tothe schedule table, is stored beginning at memory location M12. Aftercompleting the addressing corresponding to the first of the whitebitplanes, W3, and after waiting the actuation time, the controllercauses the white lamp to be illuminated for the first time.

Because all the bitplanes are to be illuminated for a period longer thanthe time it takes to load a bitplane into the array of light modulators726, the controller 704 extinguishes the lamp illuminating a sub-frameimage upon completion of an addressing event corresponding to thesubsequent sub-frame image. For example, LT0 is set to occur at a timeafter AT0 which coincides with the completion of the loading of bitplaneR2. LT1 is set to occur at a time after AT1 which coincides with thecompletion of the loading of bitplane R1.

The time period between vsync pulses in the timing diagram is indicatedby the symbol FT, indicating a frame time. In some implementations theaddressing times AT0, AT1, etc. as well as the lamp times LT0, LT1, etc.are designed to accomplish 4 sub-frame images for each of the 4 colorswithin a frame time FT of 16.6 milliseconds, i.e. according to a framerate of 60 Hz. In other implementations the time values stored inschedule table store 726 can be altered to accomplish 4 sub-frame imagesper color within a frame time FT of 33.3 milliseconds, i.e. according toa frame rate of 30 Hz. In other implementations frame rates as low as 24Hz may be employed or frame rates in excess of 100 Hz may be employed.

TABLE 6 Schedule Table 6 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n addressing time AT0 AT1 AT2 AT3 AT4AT5 AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M4M6 - - - M(n − 1) Mn sub-frame data set lamp ID R R R R G G G - - - W W

The use of white lamps can improve the efficiency of the display. Theuse of four distinct colors in the sub-frame images requires changes tothe data processing in the input processing module 718. Instead ofderiving bitplanes for each of 3 different colors, a display processaccording to timing diagram 1600 requires bitplanes to be storedcorresponding to each of 4 different colors. The input processing module718 may therefore convert the incoming pixel data, encoded for colors ina 3-color space, into color coordinates appropriate to a 4-color spacebefore converting the data structure into bitplanes.

In addition to the red, green, blue, and white lamp combination, shownin timing diagram 1600, other lamp combinations are possible whichexpand the space or gamut of achievable colors. A useful 4-color lampcombination with expanded color gamut is red, blue, true green (about520 nm) plus parrot green (about 550 nm). Another 5-color combinationwhich expands the color gamut is red, green, blue, cyan, and yellow. A5-color analogue to the well known YIQ color space can be establishedwith the lamps white, orange, blue, purple, and green. A 5-color analogto the well known YUV color space can be established with the lampswhite, blue, yellow, red, and cyan.

Other lamp combinations are possible. For instance, a useful 6-colorspace can be established with the lamp colors red, green, blue, cyan,magenta, and yellow. A 6-color space can also be established with thecolors white, cyan, magenta, yellow, orange, and green. A large numberof other 4-color and 5-color combinations can be derived from amongstthe colors already listed above. Further combinations of 6, 7, 8 or 9lamps with different colors can be produced from the colors listedabove, Additional colors may be employed using lamps with spectra whichlie in between the colors listed above.

FIG. 17 is a timing diagram 1700 that corresponds to anotherimplementation of the display process 1100 that utilizes the parameterslisted in the schedule table of Table 7. The timing diagram 1700corresponds to a hybrid coded-time division and intensity grayscaledisplay process in which lamps of different colors may be illuminatedsimultaneously. Though each sub-frame image is illuminated by lamps ofall colors, sub-frame images for a specific color are illuminatedpredominantly by the lamp of that color. For example, duringillumination periods for red sub-frame images, the red lamp isilluminated at a higher intensity than the green lamp and the blue lamp.As brightness and power consumption are not linearly related, usingmultiple lamps each at a lower illumination level operating mode mayrequire less power than achieving that same brightness using one lamp atan higher illumination level.

The addressing timing is similar to that described in FIG. 12 in thateach sub-frame image is displayed at the same intensity for half as longa time period as the prior sub-frame image, except for the sub-frameimages corresponding to the least significant bitplanes which areinstead each illuminated for the same length of time as the priorsub-frame image, but at half the intensity. As such, the sub-frameimages corresponding to the least significant bitplanes are illuminatedfor a period of time equal to or longer than that required to load abitplane into the array.

TABLE 7 Schedule Table 7 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n data time AT0 AT1 AT2 AT3 AT4 AT5AT6 - - - AT(n − 1) ATn memory location of M0 M1 M2 M3 M4 M5 M6 - - -M(n − 1) Mn sub-frame data set red average RI0 RI1 RI2 RI3 RI4 RI5RI6 - - - RI(n − 1) Rn intensity green average GI0 GI1 GI2 GI3 GI4 GI5GI6 - - - GI(n − 1) Gn intensity blue average BI0 BI1 BI2 BI3 BI4 BI5BI6 - - - BI(n − 1) Bn intensity

More specifically, the display of an image frame in timing diagram 1700begins upon the detection of a vsync pulse. As indicated on the timingdiagram and in the Table 7 schedule table, the bitplane R3, storedbeginning at memory location M0, is loaded into the array of lightmodulators 702 in an addressing event that begins at time AT0. Once thecontroller 704 outputs the last row data of a bitplane to the array oflight modulators 702, the controller 704 outputs a global actuationcommand. After waiting the actuation time, the controller causes thered, green and blue lamps to be illuminated at the intensity levelsindicated by the Table 7 schedule, namely RI0, GI0 and BI0,respectively. Similar to the addressing process described with respectto FIG. 12, since the actuation time is a constant for all sub-frameimages, no corresponding time value needs to be stored in the scheduletable store 726 to determine this time. At time AT1, the controller 704begins loading the subsequent bitplane R2, which, according to theschedule table, is stored beginning at memory location M1, into thearray of light modulators 702. The sub-frame image corresponding tobitplane R2, and later the one corresponding to bitplane R1, are eachilluminated at the same set of intensity levels as for bitplane R1, asindicated by the Table 7 schedule. In comparison, the sub-frame imagecorresponding to the least significant bitplane R0, stored beginning atmemory location M3, is illuminated at half the intensity level for eachlamp. That is, intensity levels RI3, GI3 and BI3 are equal to half thatof intensity levels RI0, GI0 and BI0, respectively. The processcontinues starting at time AT4, at which time bitplanes in which thegreen intensity predominates are displayed. Then, at time AT8, thecontroller 704 begins loading bitplanes in which the blue intensitydominates.

Because all the bitplanes are to be illuminated for a period longer thanthe time it takes to load a bitplane into the array of light modulators726, the controller 704 extinguishes the lamp illuminating a sub-frameimage upon completion of an addressing event corresponding to thesubsequent sub-frame image. For example, LT0 is set to occur at a timeafter AT0 which coincides with the completion of the loading of bitplaneR2. LT1 is set to occur at a time after AT1 which coincides with thecompletion of the loading of bitplane R1.

The mixing of color lamps within sub-frame images in timing diagram 1700can lead to improvements in power efficiency in the display. Colormixing can be particularly useful when images do not include highlysaturated colors.

FIG. 18 is a more detailed flow chart of an illustrative display process1800 suitable for use as part of the display method 800 for displayingimages on the direct-view display 700. As in the display process 1100,the display process 1800 utilizes bitplanes for sub-frame data sets.Display process 1800 also includes a global actuation functionalitysimilar to that used in display process 1100. Display process 1800,however, adds a bankwise addressing functionality as a tool forimproving the illumination efficiency in the display.

For many display processes, especially where a display loads anddisplays large numbers of bitplanes (for example, greater than 5) foreach color component of an image, proportionately more time must bededicated to the addressing of the display at the expense ofillumination of corresponding sub-images This is true even when globalactuation techniques are employed as in display process 1100. Thesituation is illustrated by the timing diagram 1400 of FIG. 14A. Timingdiagram 1400 illustrates a 5-bit sequence per color with illuminationvalues assigned to the bitplanes according to a binary significancesequence 16:8:4:2:1. The illumination periods associated with thebitplanes R1 and R0, however, are considerably shorter than the timerequired for loading data sets into the array appropriate to the nextbitplane. As a result, a considerable amount of time passes between thetimes the lamps illuminating the R1 and R0 bitplanes are extinguishedand the times the lamps illuminating the R0 and G4 bitplanes,respectively, are turned on. This situation results in a reduced dutycycle and therefore reduced efficiency for lamp illumination.

Bankwise addressing is a functionality by which duty cycles for lampscan be increased by reducing the times required for addressing. This isaccomplished by dividing the display into multiple independentlyactuatable banks of rows such that only a portion of the display needsto be addressed and actuated at any one time. Shorter addressing cyclesincrease the efficiency of the display for those bitplanes that requireonly the shortest of illumination times.

In one particular implementation, bank-wise addressing involvessegregating the rows of the display into two segments. In oneembodiment, the rows in the top half of the display are controlledseparately from rows in the bottom half of the display. In anotherembodiment the display is segregated on an every-other row basis, suchthat even-numbered rows belong to one bank or segment and theodd-numbered rows belong to the other bank. Separate bitplanes arestored for each segment at a distinct addresses in the buffer memory722. For bank-wise addressing, the input processing module 718 isprogrammed to not only derive bitplane information from the incomingvideo stream, but also to identify, and in some cases store, portions ofbitplanes separately according to their assignment to different banks Inthe following description bitplanes are labeled by color, bank, andsignificance value. For example, bitplane RE3 in a five bit per colorcomponent gray scale process refers to the second most significantbitplane for the even numbered rows of the display apparatus. BitplaneBO0 corresponds to the least significant blue bitplane for the oddnumbered rows.

When the bankwise addressing scheme employs a global actuationfunctionality, then independent global actuation voltage drivers andindependent global actuation interconnects are provided for each bank.For instance the odd-numbered rows are connected to one set of globalactuation drivers and global actuation interconnects, while the evennumbered rows are connected to an independent set of global actuationdrivers and interconnects.

Display process 1800 begins with the initiation of the display of a newimage frame (step 1802). Such an initiation may be triggered by thedetection of a vsync voltage pulse in the image signal 717. Then, at atime identified in the schedule table store 726 after the initiation ofthe display process for the image frame, the controller 704 beginsloading the first bitplane into the light modulators of the array oflight modulators 702 (step 1804). In contrast to step 1104 of FIG. 11,at step 1804, bitplanes for either one or both of the banks of thedisplay are loaded into the corresponding rows of the array of lightmodulators 702. In one embodiment, at step 1804, the timing controlmodule 724 analyzes its output sequence to see how many banks need to beaddressed in a given addressing event and then addresses each bankneeded to be addressed in sequence. In one implementation, for one bank,bitplanes are loaded into corresponding light modulator rows in order ofincreasing significance while for the other bank, bitplanes are loadedinto the corresponding light modulator rows in order of decreasingsignificance.

At step 1806, any lamp currently illuminated is extinguished. Step 1806may occur at or before the loading of a particular bitplane (step 1804)is completed, depending on the significance of the bitplane. Forexample, in some embodiments, to maintain the binary weighting ofbitplanes with respect to one another, some bitplanes may need to beilluminated for a time period that is less than the amount of time ittakes to load the next bitplane into the array of light modulators 702.Thus, a lamp illuminating such a bitplane is extinguished while the nextbitplane is being loaded into the array of light modulators (step 1804).To ensure that lamps are extinguished at the appropriate time, a timingvalue is stored in the schedule table to indicate the appropriate lightextinguishing time.

When the controller 704 has completed loading either or both of thebitplane data into either or both of banks in the array of lightmodulators 702 (step 1804) and when the controller has extinguished anyilluminated lamps (step 1806), the controller 704 issues a globalactuation command (step 1808) to either or both of the global actuationdrivers, depending on where it is in its output sequence, therebycausing either only one of the banks of addressable modulators or bothbanks in the array of light modulators 702 to actuate at substantiallythe same time. The timing of the global actuation is determined by logicin the timing control module based on whether the schedule indicatesthat one or both of the banks requires addressing. That is, if a singlebank needs addressing according to the schedule table store 726, thetiming control module 724 waits a first amount of time before causingthe controller 704 to issue the global actuation command. If theschedule table store 726 indicates both banks require addressing, thetiming control module 724 waits about twice that amount of time beforetriggering global actuation. As only two possible time values are neededfor timing global actuation (i.e., a single bank time, or a dual banktime), these values can be stored permanently in the timing controlmodule 724 in hardware, firmware, or software.

After waiting the actuation time of the light modulators, the controller704 issues an illumination command (step 1810) to the lamp drivers toturn on the lamp corresponding to the recently loaded bitplane. Theactuation time is measured from the time a global actuation command isissued (step 1808), and thus is the same for each bitplane loaded.Therefore, it need not be stored in a schedule table. It can bepermanently stored in the timing control module 724 in hardware,firmware, or software.

After the lamp corresponding to the bitplane is illuminated (step 1810),at decision block 1812, the controller 704 determines, based on theschedule table store 726, whether the currently loaded bitplane is thelast bitplane for the image frame to be displayed. If so, the controller704 awaits initiation of the display of a subsequent image frame (step1802). Otherwise, at the time of the next addressing event listed in theschedule table store 726, the controller 704 begins loading thecorresponding bitplane or bitplanes into the array of light modulators702 (step 1804).

FIG. 19 is a timing diagram 1900 that corresponds to an implementationof the display process 1800 through utilization of the parameters listedin the schedule table of Table 8. The timing diagram 1900 corresponds toa coded-time division grayscale display process in which image framesare displayed by displaying 5 sub-frame images for each of three colorcomponents (red, green, and blue) of the image frame. Each sub-frameimage displayed of a given color is displayed at the same intensity forhalf as long a time period as the prior sub-frame image, therebyimplementing a binary weighting scheme for the sub-frame images. Inaddition, the timing diagram 1900 incorporates the global actuationfunctionality described in the display process 1100 and the bankwiseaddressing functionality described in the display process 1800. Byreducing the times required for addressing, the display can thereforeeither display brighter images, or it can operate its lamps at lowerpower levels while maintaining the same brightness level. As brightnessand power consumption are not linearly related, the lower illuminationlevel operating mode, while providing equivalent image brightness,consumes less energy.

TABLE 8 Schedule Table 8 Field Field Field Field Field Field Field FieldField 1 2 3 4 5 6 7 - - - n − 1 n data time AT0 AT1 AT2 AT3 AT4 AT5AT6 - - - AT(n − 1) ATn memory location for MO0 0 0 0 0 MO5 M06 - - -MO(n − 1) MOn Bank 1 “odd rows” memory location for ME0 ME1 ME2 ME3 ME40 0 - - - ME(n − 1) MEn Bank 2 “even rows” lamp ID R R R R R R R - - - BB lamp time LT0 LT1 LT2 LT3 LT4 LT5 LT6 - - - LT(n − 1) LTn

More specifically, the display of an image frame in timing diagram 1900begins upon the detection of a vsync pulse. As indicated on the timingdiagram and in the Table 8 schedule table, the bitplane RO4, storedbeginning at memory location MO0, is loaded into only the odd rows ofthe array of light modulators 702 in an addressing event that begins attime AT0. Immediately thereafter, the bitplane RE1 is loaded into onlythe even rows of the array of light modulators, using data stored in thelocation ME0. Once the controller 704 outputs the last of the even rowsof data of a bitplane to the array of light modulators 702, thecontroller 704 outputs a global actuation command to both of theindependently addressable global actuation drivers connected to thebanks of even and odd rows. After waiting the actuation time followingthe issuance of the global actuation command, the controller 704 causesthe red lamp to be illuminated. As indicated above, since the actuationtime is a constant for all sub-frame images and is based on the issuanceof the global actuation command, no corresponding time value needs to bestored in the schedule table store 726 to determine this time.

At time AT1, the controller 704 begins loading the subsequent bitplaneRE0, stored beginning at memory location ME1, into the even rows of thearray of light modulators 702. During the addressing event beginning atAT1, the timing control module 724 skips any process related to loadingof the data into the odd rows. This may be accomplished by storage of acoded parameter in the schedule table store 726 associated with thetiming value AT1, for instance, the numeral zero. In this fashion theamount of time to complete the addressing event initiated at time AT1 isonly ½ of the time required for addressing both banks of rows at timeAT0. Note that the least significant red bitplane for the odd rows isnot loaded into the array of light modulators 702 until much later, attime AT5.

Lamp extinguishing event times LT0-LTn−1 occur at times stored in theschedule table store 726. The times may be stored in terms of clockcycles following the detection of a vsync pulse, or they may be storedin terms of clock cycles following the beginning of the loading of theprevious bitplane into the array of light modulators 702. For bitplaneswhich are to be illuminated for a period longer than the time it takesto load a bitplane into the array of light modulators 726, the lampextinguishing times are set in the schedule table to coincide with thecompletion of a corresponding addressing event. For example, LT0 is setto occur at a time after AT0 which coincides with the completion of theloading of the even-numbered rows. LT0 is set to occur at a time afterAT1 which coincides with the completion of the loading of bitplane RE0into the even-numbered rows. LT3 is set to occur at a time after AT4,which coincides with the completion of the loading of bitplane RO1 intothe odd-numbered rows. After all red bitplanes for each bank are loadedand illuminated for the appropriate amounts of time, the process beginsagain with the green bitplanes.

The example of bank-wise addressing by timing diagram 1900 provides foronly two independently addressable and actuatable banks. In otherembodiments, arrays of MEMS modulators and their drive circuits can beinterconnected so as to provide 3, 4, 5, 6, 7, 8 or more independentlyaddressable banks A display with 6 independently addressable banks wouldrequire only ⅙ the time for addressing the rows within one bank, incomparison to time needed for addressing of the whole display. With theuse of 6 banks, 6 different bitplanes attributed to the same color oflamp can be interleaved and illuminated simultaneously. For the 6-bitexample, the rows associated with each bank may be assigned to every6^(th) row of the display.

In some embodiments that employ bank-wise addressing, it is notnecessary to turn off the lamps while switching a given bank of rowsfrom states indicated by one bitplane to states indicated in the next,as long as the states of the rows in the other contemporaneous banks areassociated with the same color.

Referring again to the sequencing rules introduced with respect totiming diagram 1500, the bank-wise addressing scheme provides additionalopportunities for reducing flicker in a MEMS-based field sequentialdisplay. In particular the red bitplane R1 for the even rows, introducedat addressing event AT0, is displayed within the same grouping of redsub-images as the red bitplane R1 for the odd rows, introduced at timingevent AT4. Each of these bitplanes is displayed only once per frame. Ifthe frame rate in timing diagram 19 was as low as 30 Hz, then thedisplay of these lesser bitplanes would be separated by substantiallymore than 25 milliseconds between frames, contributing to the perceptionof flicker. However, this situation can be improved if the bitplanes intiming diagram 19 are further re-arranged such that the display of R1bitplanes between adjacent frames are never separated by more than 25milliseconds, preferably less than 17 milliseconds.

In particular, the display of the most significant bitplane in red, i.e.the most significant bit—R4, can be split, for instance at some pointbetween the addressing events AT3 and AT4. The two groupings of redsub-images can then be re-arranged amongst similar sub-groupings in thegreen and blue sub-images. The red, green, and blue sub-groupings can beinterspersed, as in the timing diagram 1500. The result is that that thedisplay of the e.g. R1, G1, B1, sub-frame data sets can be arranged toappear at roughly equal time intervals, both within and betweensuccessive image frames. In this example, the R1 bitplane for the evenrows would still appear only once per image frame. Flicker can bereduced, however, if the display of the R1 bitplane alternates betweenodd and even rows, and if the time separation between display of the oddor even portions of the bitplane is never more than 25 milliseconds,preferably less than 17 milliseconds.

FIG. 20 is a block diagram of a controller 2000 for use in a direct-viewdisplay, according to an illustrative embodiment of the invention. Forexample, the controller 2000 can replace the controller 704 of thedirect-view MEMS display 700 of FIG. 7. The controller 2000 receives animage signal 2017 from an external source and outputs both data andcontrol signals for controlling light modulators and lamps of thedisplay into which it is incorporated

The controller 2000 includes an input processing module 2018, a memorycontrol module 2020, a frame buffer 2022, a timing control module 2024,four unique schedule table stores 2026, 2027, 2028, and 2029. For thecontroller 2000, instead of a programming link which allows alterationof the parameters in a schedule table store, the controller provides aswitch control module 2040 which determines which of the 4 scheduletable stores will be active at any given time. In some implementationsthe components 2018-2040 may be provided as distinct chips or circuitswhich are connected together by means of circuit boards and/or cables.In other implementations several of these components can be designedtogether into a single semiconductor chip such that their boundaries arenearly indistinguishable except by function.

The input processing module 2018 receives the image signal 2017 andprocesses the data encoded therein, similar to input processing module718, into a format suitable for displaying via the array of lightmodulators. The input processing module 2018 takes the data encodingeach image frame and converts it into a series of sub-frame data sets.While in various embodiments, the input processing module 2018 mayconvert the image signal 2017 into non-coded sub-frame data sets,ternary coded sub-frame data sets, or other form of coded sub-frame dataset, preferably, the input processing module 2018 converts the imagesignal 2017 into bitplanes, as described above in relation to FIGS.6A-6C.

The input processing module 2018 outputs the sub-frame data sets to thememory control module 2020. The memory control module 2020 then storesthe sub-frame data sets in the frame buffer 2022. The frame buffer ispreferably a random access memory, although other types of serial memorycan be used without departing from the scope of the invention. Thememory control module 2020, in one implementation stores the sub-framedata set in a predetermined memory location based on the color andsignificance in a coding scheme of the sub-frame data set. In otherimplementations, the memory control module 2020 stores the sub-framedata set in a dynamically determined memory location and stores thatlocation in a lookup table for later identification. In one particularimplementation, the frame buffer 2022 is configured for the storage ofbitplanes.

The memory control module 2020 is also responsible for, upon instructionfrom the timing control module 2024, retrieving sub-image data sets fromthe frame buffer 2022 and outputting them to the data drivers. The datadrivers load the data output by the memory control module 2020 into thelight modulators of the array of light modulators. The memory controlmodule 2020 outputs the data in the sub-image data sets one row at atime. In one implementation, the frame buffer 2022 includes two buffers,whose roles alternate. While the memory control module 2020 stores newlygenerated bitplanes corresponding to a new image frame in one buffer, itextracts bitplanes corresponding to the previously received image framefrom the other buffer for output to the array of light modulators Bothbuffer memories can reside within the same circuit, distinguished onlyby address.

The order in which the sub-image data sets are output, referred to asthe “sub-frame data set output sequence,” and the time at which thememory control module 2022 begins outputting each sub-image data set iscontrolled, at least in part, by data stored in one of the alternateschedule table stores 2026, 2027, 2028, and 2029. Each of the scheduletable stores 2026-2029 stores at least one timing value associated witheach sub-frame data set, an identifier indicating where the sub-imagedata set is stored in the frame buffer 2022, and illumination dataindicating the color or colors associated with the sub-image data set.In some implementations, the schedule table stores 2026-2029 also storeintensity values indicating the intensity with which the correspondinglamp or lamps should be illuminated for a particular sub-frame data set.

In one implementation the timing values stored in the schedule tablestores 2026-2029 determine when to begin addressing the array of lightmodulators with the sub-frame data set. In another implementation, thetiming value is used to determine when a lamp or lamps associated withthe sub-frame data set should be illuminated and/or extinguished. In oneimplementation, the timing value is a number of clock cycles, which forexample, have passed since the initiation of the display of an imageframe, or since the last addressing or lamp event was triggered.Alternatively, the timing value may be an actual time value, stored inmicroseconds or milliseconds.

The distinct timing values stored in the various schedule table stores2026-2029 provide a choice between distinct imaging algorithms, forinstance between display modes which differ in the properties of framerate, lamp brightness, achievable grayscale precision, or in thesaturation of displayed colors. The storage of multiple schedule tables,therefore, provides for flexibility in the method of displaying images,a flexibility which is especially advantageous when it provides a methodfor saving power for use in portable electronics. Direct view display2000 includes 4 unique schedule tables stored in memory. In otherimplementations the number of distinct schedules that are stored may be2, 3, or any other number. For instance it may be advantageous to storeschedule parameters for as many as 100 unique schedule table stores.

The multiple schedule tables stored in controller 2000 allow for theexploitation of trade-offs between image quality and power consumption.For some images, which do not require a display of deeper, saturatedcolors, it is possible to rely on white lamps or mixed colors to providebrightness, especially as these color schemes can be more powerefficient. Similarly, not all images or applications require the displayof 16 million colors. A palette of 250,000 colors may be sufficient (6bits per color) for some images or applications. For other images orapplications, a color range limited to only 4,000 colors (4 bits percolor) or 500 colors (3 bits per color) may be sufficient. It isadvantageous to include electronics in a direct view MEMS displaycontroller so as to provide display flexibility to take advantage ofpower saving opportunities.

Many of the variables effecting both image quality and power consumptionin a MEMS direct view display are governed by the timing and bitplaneparameters which are stored in the schedule table store stores2026-2029. Together with the sequencing commands stored within thetiming control module 2024, these parameters allow the controller 2000to output variations on lamp intensities, frame rates, different palletsof colors (based on the mixing of lamp colors within a subfield), ordifferent grey scale bit depths (based on the number of bitplanesemployed to display an image frame).

In one implementation, each schedule table corresponds to a differentdisplay process. For example, schedule table 2026 corresponds to adisplay process capable of generating approximately 16 million colors (8bits per color) with high color saturation. Schedule table 2027corresponds to a display process appropriate only for black and white(e.g. text) images with a frame rate, or refresh rate, that is very low,e.g. less than 20 frames per second. Schedule table 2028 corresponds toa display process suited for outdoor viewing of color or video imageswhere brightness is at a premium but where battery power mustnevertheless be conserved. Schedule table 2029 corresponds to a displayprocess providing a restricted choice of colors (e.g. 4,000) which wouldprovide an easy to read and low-power display appropriate for most iconor text-type information with the exception of video. Of the displayprocesses represented by the schedule table stores 2026-2029, thedisplay process represented by schedule table 2026 requires the mostpower, whereas the display process represented by schedule table 2027requires the least. The display processes corresponding to scheduletables 2028 and 2029 require power usage somewhere in between thatrequired by the other display processes.

In the controller 2000, for any given image frame, the timing controlmodule 2024 derives its display process parameters or constants fromonly one of the four possible sequence tables. A switch control module2040 governs which of the sequence tables is referenced by the timingcontrol module 2040. This switch control module 2040 could be a usercontrolled switch, or it could be responsive to commands from anexternal processor, contained either within the same housing as the MEMSdisplay device or external to it (referred to as an “external module”).The external module, for instance, can decide whether the information tobe displayed is text or video, or whether the information displayedshould be colored or strictly black and white. In some embodiments theswitch commands can originate from the input processing module 2018.Whether in response to an instruction from the user or an externalmodule, the switch control module 2040 selects a schedule table storethat corresponds to the desired display process or display parameters.

FIG. 21 is a flow chart of a process of displaying images 2100 (the“display process 2100”) suitable for use by a direct-view display suchas the controller 2000 of FIG. 20, according to an illustrativeembodiment of the invention. Referring to FIGS. 20 and 21, the displayprocess 2100 begins with the selection of an appropriate schedule tablefor use in displaying an image frame (step 2102). For example, aselection is made between schedule table stores 2026-2029. Thisselection can be made by the input processing module 2118, a module inanother part of the device in which the direct-view MEMS display isincorporated, or it can be made directly by the user of the device. Whenthe selection amongst schedule tables is made by the input processingmodule or an external module, it can be made in response to the type ofimage to be displayed (for instance video or still images require finerlevels of gray scale contrast versus an image which needs only a limitednumber of contrast levels (such as a text image)). Another factor whichthat might influence the selection of an imaging mode or schedule table,whether selected directly by a user or automatically by the externalmodule, might be the lighting ambient of the device. For example, onemight prefer one brightness for the display when viewed indoors or in anoffice environment versus outdoors where the display must compete in anenvironment of bright sunlight. Brighter displays are more likely to beviewable in an ambient of direct sunlight, but brighter displays consumegreater amounts of power. The external module, when selecting scheduletables on the basis of ambient light, can make that decision in responseto signals it receives through an incorporated photodetector. Anotherfactor that might influence the selection of an imaging mode or scheduletable, whether selected directly by a user or automatically by theexternal module, might be the level of stored energy in a batterypowering the device in which the display is incorporated. As batteriesnear the end of their storage capacity it may be preferable to switch toan imaging mode which consumes less power to extend the life of thebattery.

The selection step 2102 can be accomplished by means of a mechanicalrelay, which changes the reference within the timing control module 2024to only one of the four schedule table stores 2026-2029. Alternately,the selection step 2102 can be accomplished by the receipt of an addresscode which indicates the location of one of the schedule table stores2026-2029. The timing control module 2024 then utilizes the selectionaddress, as received through the switch control module 2040, to indicatethe correct memory source for its schedule parameters. Alternately thetiming control module 2024 can make reference to a schedule table storedin memory by means of a multiplexer circuit, similar to a memory controlcircuit. When a selection code is entered into the controller 2000 bymeans of the switch control module 2040, the multiplexer is reset sothat schedule table parameters requested by the timing control module2024 are routed to the correct address in memory.

The process 2100 then continues with the receipt of the data for animage frame. The data is received by the input processing module 2018 bymeans of the input line 2017 at step 2104. The input processing modulethen derives a plurality of sub-frame data sets, for instance bitplanes,and stores them in the frame buffer 2022 (step 2106). After storage ofthe sub-frame data sets the timing control module 2024 proceeds todisplay each of the sub-frame data sets, at step 2108, in their properorder and according to timing values stored in the selected scheduletable.

The process 2100 then continues iteratively with receipt of subsequentframes of image data. The sequence of receiving image data at step 2104through the display of the sub-frame data sets at step 2108 can berepeated many times, where each image frame to be displayed is governedby the same selected schedule table. This process can continue until theselection of a new schedule table is made at a later time, e.g. byrepeating the step 2102. Alternatively, the input processing module 2018may select a schedule table for each image frame received, or it mayperiodically examine the incoming image data to determine if a change inschedule table is appropriate.

FIG. 22 is a block diagram of a controller 2200, suitable for inclusionin a MEMS direct-view display, according to an illustrative embodimentof the invention. For example, the controller 2200 may replace thecontroller 704 of the MEMS direct-view display 700. The controller 2200receives an image signal 2217 from an external source and outputs bothdata and control signals for controlling the drivers, light modulators,and lamps of the display in which the controller is included.

The controller 2200 includes an input processing module 2218, a memorycontrol module 2220, a frame buffer 2222, a timing control module 2224.In contrast to controllers 704 and 2000, the controller 2200 includes asequence parameter calculation module 2228. The sequence parametercalculation module receives monitoring data from the input processingmodule 2218 and outputs changes to the sequencing parameters storedwithin the schedule table store 2226, and in some implementations,changes to the bitplanes stored for a given image frame. In someimplementations, the components 2218, 2220, 2222, 2224, 2226, and 2228may be provided as distinct chips or circuits which are connectedtogether by means of circuit boards and/or cables. In otherimplementations, several of these components can be designed togetherinto a single semiconductor chip such that their boundaries are nearlyindistinguishable except by function.

The input processing module 2218 receives the image signal 2217 andprocesses the data encoded therein into a format suitable for displayingvia the array of light modulators. The input processing module 2218takes the data encoding each image frame and converts it into a seriesof sub-frame data sets. A sub-frame data set includes information aboutthe desired states of modulators in multiple rows and multiple columnsof the array of light modulators. The number and content of sub-framedata sets used to display an image frame depends on the grayscaletechnique employed by the controller 2200. For example, the sub-framedata sets needed to form an image frame using a coded time-division grayscale technique differs from the number and content of sub-frame datasets used to display an image frame using a non-coded time division grayscale technique. While in various embodiments, the input processingmodule 2218 may convert the image signal 2217 into non-coded sub-framedata sets, ternary coded sub-frame data sets, or other form of codedsub-frame data set, preferably, the input processing module 2218converts the image signal 2217 into bitplanes, as described above inrelation to FIGS. 6A-6C.

The input processing module 2218 outputs the sub-frame data sets to thememory control module 2220. The memory control module 2220 then storesthe sub-frame data sets in the frame buffer 2222. The memory controlmodule 2220, in one implementation stores the sub-frame data set in apredetermined memory location based on the color and significance in acoding scheme of the sub-frame data set. In other implementations, thememory control module 2220 stores the sub-frame data set in adynamically determined memory location and stores that location in alookup table for later identification. In one particular implementation,the frame buffer 2222 is configured for the storage of bitplanes.

The memory control module 2220 is also responsible for, upon instructionfrom the timing control module 2224, retrieving bitplanes sets from theframe buffer 2222 and outputting them to the data drivers 2208. The datadrivers 2208 load the data output by the memory control module 2220 intothe light modulators of the array of light modulators. The memorycontrol module 2220 outputs the data in the sub-image data sets one rowat a time. In one implementation, the frame buffer 2222 includes twobuffers, whose roles alternate. While the memory control module 2220stores newly generated bitplanes corresponding to a new image frame inone buffer, it extracts bitplanes corresponding to the previouslyreceived image frame from the other buffer for output to the array oflight modulators Both buffer memories can reside within the samecircuit, distinguished only by address.

The order in which the sub-image data sets are output, referred to asthe “sub-frame data set output sequence,” and the time at which thememory control module 2220 begins outputting each sub-image data set iscontrolled, at least in part, by data stored in the schedule table store2226. The schedule table store 2226 stores at least one timing valueassociated with each sub-frame data set, an identifier indicating wherethe sub-image data set is stored in the frame buffer 2222, andillumination data indicating the color or colors associated with thesub-image data set. In some implementations, the schedule table store2226 also stores intensity values indicating the intensity with whichthe corresponding lamp or lamps should be illuminated for a particularsub-frame data set.

In one implementation the timing values stored in the schedule tablestore 2226 determine when to begin addressing the array of lightmodulators with each sub-frame data set. In another implementation, thetiming value is used to determine when a lamp or lamps associated withthe sub-frame data set should be illuminated and/or extinguished. In oneimplementation, the timing value is a number of clock cycles, which forexample, have passed since the initiation of the display of an imageframe, or since the last addressing or lamp event was triggered.Alternatively, the timing value may be an actual time value, stored inmicroseconds or milliseconds.

Controller 2200 includes a re-configurable schedule table store 2226. Asdescribed above with respect to controllers 704 and 2000 the scheduletable store 2226 provides a flexible or programmable component to thecontroller. A programming link, such as the interface 730 allowed theschedule table store 726 within controller 704 to be altered orreprogrammed according to different lamp intensities, frame rates, colorschemes, or grey scale bit depths. Similar alterations to the displayprocess are possible for schedule table store 2226 within controller2200, except that these variations now occur automatically in responseto the requirements of individual image frames, based on characteristicsof those image frames detected by the input processing module 2218

Based on the data contained within the image frame, it is often possibleto reduce power consumption in the display by controlling variables suchas lamp brightness, color saturation, and bit depth without any changeor distortion perceptible in the image. This is because many images donot require full brightness from the lamps, or they do not require thedeepest or most saturated of colors, or they require only a limitednumber of gray scale levels. Controller 2200 is configured to sense thedisplay requirements for an image frame based on the data within theimage frame and to adapt the display algorithm by means of changes tothe schedule table store 2226.

A method by which the controller 2200 can adapt the displaycharacteristics based on the content of incoming image data is shown inFIG. 23 as display method 2300. Display method 2300 is suitable for useby a MEMS direct-view display such as the MEMS direct-view display 2200of FIG. 22, according to an illustrative embodiment of the invention.Referring to FIGS. 22 and 23, the display method 2300 begins with thereceipt of the data for an image frame at step 2302. The data isreceived by the input processing module 2218 by means of the input line2217. The input processing module 2218 derives a plurality of sub-framedata sets, for instance bitplanes, from the data and stores thebitplanes in the frame buffer 2222. Additionally, however, at step 2304prior to the storage of the bitplanes in step 2306, the input processingmodule monitors and analyzes the content of the incoming image to lookfor characteristics which might effect the display of that image. Forinstance at step 2304 the input processing module might make note of thepixel or pixels with the most saturated colors in the image frame, i.e.pixels which call for significant brightness values from one color whichare not balanced, diluted or desaturated by requiring illumination inthe same pixel from the other color lamps in the same image frame. Inanother example of input data monitoring, the input processing module2218 might make note of the pixel or pixels with the brightest valuesrequired of each of the lamps, regardless of color saturation.

After a complete image frame has been received and stored in the framebuffer 2222 the method 2300 proceeds to step 2308. At step 2308 thesequence parameter calculation module 2228 assesses the data collectedat step 2304 and identifies changes to the display process that can beimplemented by adjusting values in the sequence table 2226. The changesto the sequence table 2226 are then affected at step 2310 by re-writingcertain of the parameters stored within table 2226. Finally, at step2312, the method 2300 proceeds to the display of sub-images according tothe ordering parameters and timing values that have been re-programmedwithin the schedule table 2226.

The method 2300 then continues iteratively with receipt of subsequentframes of image data. As indicated in the method 800, the processes ofreceiving (step 2302) and displaying image data (step 2312) may run inparallel, with one image being displayed from the data of one buffermemory according to the re-programmed schedule table at the same timethat new sub-frame data sets are being analyzed and stored into aparallel buffer memory. The sequence of receiving image data at step2302 through the display of the sub-frame data sets at step 2312 can berepeated interminably, where each image frame to be displayed isgoverned by a schedule table which is re-programmed in response to theincoming data.

It is instructive to consider some examples of how the method 2300 canreduce power consumption by adjusting the display characteristics in theschedule table store 2226 in response to data collected at step 2304.These examples are referred to as adaptive power schemes.

In one scheme for adaptive power that is responsive to the incomingimage data, the data monitoring at step 2304 detects the pixels in eachframe with the most saturated colors. If it is determined that the mostsaturated color required for a frame is only 82% of the saturationavailable from the colored lamps, then it is possible to remix thecolors that are provided to the bitplanes so that power can besaved—while still providing the 82% saturation level required by theimage. By adding, for instance subordinate red, green, or blue colors tothe primary color in each frame, power can be saved in the display. Inthis example the sequence parameter calculation module 2228 wouldreceive a signal from the input processing module 2218 indicating thedegree of color mixing which is allowed. Before the frame is displayedthe sequence parameter calculation module re-writes the intensityparameters in the sequence table 2226 which determine color mixing ateach bitplane, so that colors are correspondingly desaturated and poweris saved.

In another adaptive power scheme, a process is provided within thesequence parameter calculation module 2228 which determines whether theimage is comprised solely of text or text plus symbols as opposed tovideo or a photographic image. The sequence parameter calculation module2228 then re-writes the parameters in the sequence table accordingly.Text images, especially black and white text images, do not need to berefreshed as often as video images and typically require only a limitednumber of different colors or gray shades. The sequence parametercalculator 2228 can therefore adjust both the frame rate as well as thenumber of sub-images to be displayed for each image frame. Text imagesrequire fewer sub-images in the display process than photographic images

In still another adaptive power scheme, the monitoring function at step2304 analyzes or searches for the maximum intensity attributed to eachcolor in each pixel. If an image is to be displayed that requires nomore than 65% of the brightness from any of the lamps for any of thepixels, then in some cases it is possible to display that imagecorrectly by reducing the average intensity of the lamps accordingly.The lamp intensity values within the schedule table store 2226 can bereduced by a set of commands within the sequence parameter calculationmodule 2228.

APPENDIX 1

Appendix 1 presents a timing sequence 3000 expressed by means ofschedule table 9, which expresses an embodiment for the timing sequencesof this invention.

The timing sequence 3000 of Appendix 1 is appropriate to the display ofimage information at a 30 Hz frame rate (e.g. 33.3 milliseconds betweenvsync pulses); it includes the display of 7 bits for each of the colorsred, green, and blue. The timing sequence 3000 is constrained by thefollowing parameters related to setting of modulator states in thearray:

-   -   240 microseconds required for loading a complete bitplane to the        array    -   120 microseconds required for loading bitplanes to only a single        bank (odd or even) of rows    -   100 microseconds required for global actuation        The schedule table for timing sequence 3000 includes the        following information, required by the timing control module 724        for display of the sub-images    -   Subfield number    -   Bitplane interval (elapsed time between global actuation pulses)    -   Alphanumeric code for memory locations of the bitplanes,        separated by their assigned banks (e.g. R0, R1, R2, . . . R6)    -   Illumination intensity        The schedule table for timing sequence 3000 does not distinguish        between addressing times and illumination times. Instead the        logic within the timing control module 724 assumes that each        bitplane interval begins immediately after completion of a        global actuation event. In the first action of the sequence        after global actuation the lamps are illuminated according to        the intensity values listed in Table 9.

The timing sequence 3000 includes the following features as describedpreviously. Similar to timing sequence 1200, the display that employstiming sequence 3000 includes the capability of global actuation. Thedisplay that employs timing sequence 3000 includes two independentglobal actuation circuits, for each of the odd and even banksrespectively. The timing sequence 3000 includes a scheme for control ofthe lamps, similar to that described in timing sequence 1450, in whichboth pulse periods and pulse intensity is used to express illuminationvalue. The timing sequence 3000 is capable of mixing colors, as intiming sequence 1700, although in this embodiment only one lamp isilluminated at one time.

The timing sequence 3000 includes bank-wise addressing. The lesserbitplanes, e.g. R0, R1, R2, and R3 are always displayed successivelywithin a given bank, e.g. the odd rows, and this sequence of lesserbitplanes is illuminated at the same time that the most significant bit(e.g. R6) is illuminated in the other bank (e.g. in the even rows).

The timing sequence 3000 splits the most significant bits (e.g. R6, G6,and B6 into four separate but equally timed sub-images. The timingsequence alternates colors frequently, with a maximum period betweencolors of 1.38 milliseconds. The time between the expression of mostsignificant bits is not always equal between successive pairs of mostsignificant bits, but in no case is that period between most significantbits greater than 4.16 milliseconds.

TABLE 9 Schedule Table 9 Interval Time Odd Field IlluminationIllumination Width Load Even Number Width Intensity (ms) bitplane Loadbitplane 0 R1 R6 1 1 1 0.1301 R2 * 2 2 1 0.2602 R3 * 3 4 1 0.5203 R0 * 41 0.5 0.1301 G1 G6 5 1 1 0.1301 G2 * 6 2 1 0.2602 G3 * 7 4 1 0.5203 G0 *8 1 0.5 0.1301 B1 B6 9 1 1 0.1301 B2 * 10 2 1 0.2602 B3 * 11 4 1 0.5203B0 * 12 1 0.5 0.1301 R6 R6 13 8 1 1.0406 G6 G6 14 8 1 1.0406 B6 B6 15 81 1.0406 R5 R5 16 8 1 1.0406 G5 G5 17 8 1 1.0406 B5 B5 18 8 1 1.0406 R4R6 19 8 1 1.0406 G4 G6 20 8 1 1.0406 B4 B6 21 8 1 1.0406 R6 R1 22 1 10.1301 * R2 23 2 1 0.2602 * R3 24 4 1 0.5203 * R0 25 1 0.5 0.1301 G6 G126 1 1 0.1301 * G2 27 2 1 0.2602 * G3 28 4 1 0.5203 * G0 29 1 0.5 0.1301B6 B1 30 1 1 0.1301 * B2 31 2 1 0.2602 * B3 32 4 1 0.5203 * B0 33 1 0.50.1301 R6 R6 34 8 1 1.0406 G6 G6 35 8 1 1.0406 B6 B6 36 8 1 1.0406 R5 R537 8 1 1.0406 G5 G5 38 8 1 1.0406 B5 B5 39 8 1 1.0406 R6 R4 40 8 11.0406 G6 G4 41 8 1 1.0406 B6 B4 42 8 1 1.0406 R1 R6

1. An electromechanical device comprising: at least one light source; anarray of light blocking elements having at least two positions; and acontroller for controlling the position of the light blocking elementsand for: obtaining from a memory a plurality of sub-frame data setscorresponding to an image frame, a respective sub-frame data set beingassociated with a weight, wherein the respective sub-frame data setindicates positions of light blocking elements in at least one row andat least one column of the array of light blocking elements; driving thelight blocking elements into a first position as indicated by arespective sub-frame data set; and controlling the at least one lightsource to generate light to pass towards the light blocking elements asindicated by the respective sub-frame data based on the weight.
 2. Theelectromechanical device of claim 1, wherein the controller applies anelectrical signal to drive the light blocking elements into the firstposition for a period of time proportional to the weight.
 3. Theelectromechanical device of claim 1, wherein the controller applies anelectrical signal to illuminate the light source for a period of timeproportional to the weight.
 4. The electromechanical device of claim 3,wherein the period of time that the light source is illuminated for isless than or equal to 4 milliseconds.
 5. The electromechanical device ofclaim 1, wherein the controller applies an electrical signal toilluminate the light source with an illumination intensity proportionalto the weight.
 6. The electromechanical device of claim 1, wherein thecontroller processes data in the plurality of sub-frame data setsaccording to an output sequence stored at least partially in memory, theoutput sequence representing timing information for illuminating thelight blocking elements to form an image.
 7. The electromechanicaldevice of claim 1, comprising at least two light sources of at least twodifferent colors, wherein the controller applies electrical signals toilluminate the light sources to generate a single sub-frame imagecorresponding to a single sub-frame data set.
 8. The electromechanicaldevice of claim 1, comprising a global actuation interconnect coupled tothe array of light blocking elements for driving light blocking elementsin multiple rows and multiple columns to actuate substantiallysimultaneously.
 9. The electromechanical device of claim 1, wherein thelight blocking elements are electromechanical shutters formed on atransparent substrate, the electromechanical shutters moving transverseto the transparent substrate to modulate light.
 10. A method fordisplaying an image frame, comprising: obtaining from a memory aplurality of sub-frame data sets corresponding to an image frame, arespective sub-frame data set being associated with a weight, andindicating positions of light blocking elements in at least one row andat least one column of an array of light blocking elements formed on asubstrate; processing the plurality of sub-frame data sets according toan output sequence stored at least partially in memory to: drive thelight blocking elements into a first position indicated in a respectivesub-frame data set; and control at least one light source to generatelight to pass towards the light blocking elements as indicated by therespective sub-frame data based on the weight.
 11. The method of claim10, comprising applying an electrical signal to drive the light blockingelements into the first position for a period of time proportional tothe weight.
 12. The method of claim 10, comprising applying anelectrical signal to illuminate the light source for a period of timeproportional to the weight.
 13. The method of claim 10, comprisingapplying an electrical signal to illuminate the light source with anillumination intensity proportional to the weight.
 14. The method ofclaim 10, wherein the weight is associated with a respective sub-framedata set according to a binary coding scheme, a respective sub-framedata set being decomposed into at least a most significant sub-frameimage and a next most significant sub-frame image.
 15. The method ofclaim 14, wherein the most-significant sub-frame image contributes to adisplayed image frame twice as much as the next most significantsub-frame image.